CD74AC20,
CD54/74ACT20
Data sheet acquired from Harris Semiconductor
SCHS229A
Dual 4-Input NAND Gate
September 1998 - Revised May 2000
Features
Description
• Typical Propagation Delay
o
The CD74AC20 and ’ACT20 are dual 4-input NAND gates that
utilize Advanced CMOS Logic technology.
- 6ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
Ordering Information
PART
NUMBER
TEMP.
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
o
RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld PDIP
CD74AC20E
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
[ /Title
(CD74
AC20,
CD74
ACT20
)
CD74AC20M
CD54ACT20F3A
CD74ACT20E
CD74ACT20M
NOTES:
14 Ld SOIC
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
/Sub-
ject
- Drives 50Ω Transmission Lines
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
(Dual
4-Input
NAND
Gate)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
Advan
ced
CMOS
,Harris
Semi-
con-
ductor,
Advan
ced
TTL)
/Cre-
ator ()
Pinout
Functional Diagram
CD54ACT20
(CERDIP)
CD74AC20, CD74ACT20
(PDIP, SOIC)
1
1A
2
1B
6
1Y
4
TOP VIEW
1C
5
1D
1A
1B
1
2
3
4
5
6
7
14 V
CC
9
2A
13 2D
12 2C
11 NC
10 2B
10
2B
8
NC
1C
2Y
12
13
2C
GND = 7
V
= 14
CC
NC = 3, 11
2D
1D
1Y
9
8
2A
2Y
TRUTH TABLE
GND
INPUTS
nB nC
OUTPUTS
nA
L
nD
X
nY
H
H
H
H
L
X
L
X
X
L
X
X
X
X
X
H
X
X
X
H
L
H
H
X = Don’t Care
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
1
Copyright © 2000, Texas Instruments Incorporated