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CD54AC191 PDF预览

CD54AC191

更新时间: 2024-01-06 09:37:18
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
10页 55K
描述
Presettable Synchronous 4-Bit Binary Up/Down Counter

CD54AC191 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.76其他特性:TCO OUTPUT
计数方向:BIDIRECTIONAL系列:AC
JESD-30 代码:X-XUUC-N16负载电容(CL):50 pF
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
传播延迟(tpd):16 ns认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子位置:UPPER
触发器类型:POSITIVE EDGE最小 fmax:60 MHz
Base Number Matches:1

CD54AC191 数据手册

 浏览型号CD54AC191的Datasheet PDF文件第2页浏览型号CD54AC191的Datasheet PDF文件第3页浏览型号CD54AC191的Datasheet PDF文件第4页浏览型号CD54AC191的Datasheet PDF文件第5页浏览型号CD54AC191的Datasheet PDF文件第6页浏览型号CD54AC191的Datasheet PDF文件第7页 
CD54AC191,  
CD54ACT191  
Data sheet acquired from Harris Semiconductor  
SCHS243A  
Presettable Synchronous 4-Bit Binary  
Up/Down Counter  
October 1998 - Revised May 2000  
Features  
Description  
• Buffered Inputs  
The CD54AC191 and CD54ACT191 are asynchronously  
presettable binary up/down synchronous counters that utilize  
Advanced CMOS Logic technology. Presetting the counter to  
the number on preset data inputs (P0-P3) is accomplished  
by setting LOW the asynchronous parallel load input (PL).  
Counting occurs when PL is HIGH, Count Enable (CE) is  
LOW, and the Up/Down (U/D) input is either LOW for up-  
counting or HIGH for down-counting. The counter is incre-  
mented or decremented synchronously with the LOW-to-  
HIGH transition of the clock.  
• Typical Propagation Delay  
o
- 12.8ns at V  
= 5V, T = 25 C, C = 50pF  
A L  
CC  
• Exceeds 2kV ESD Protection MIL-STD-883, Method  
3015  
• SCR-Latchup-Resistant CMOS Process and Circuit  
Design  
• Speed of Bipolar FAST™/AS/S with Significantly  
Reduced Power Consumption  
When an overflow or underflow of the counter occurs, the  
Terminal Count (TC) output, which is LOW during counting,  
goes HIGH and remains HIGH for one clock cycle. This out-  
put can be used for look-ahead carry in high-speed cascad-  
ing (see Figure 12). The TC output also initiates the Ripple  
Clock (RC) output which, normally HIGH, goes LOW and  
remains LOW for the low-level cascaded using the Ripple  
Count output.  
• Balanced Propagation Delays  
• AC Types Feature 1.5V to 5.5V Operation and  
Balanced Noise Immunity at 30% of the Supply  
±24mA Output Drive Current  
- Fanout to 15 FAST™ ICs  
- Drives 50Transmission Lines  
Ordering Information  
Pinout  
PART  
NUMBER  
TEMP.  
CD54AC191, CD54ACT191  
(CERDIP)  
o
RANGE ( C)  
-55 to 125  
-55 to 125  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
TOP VIEW  
CD54AC191F3A  
CD54ACT191F3A  
NOTES:  
P1  
Q1  
1
2
3
4
5
6
7
8
16 V  
CC  
15 P0  
14 CP  
13 RC  
12 TC  
11 PL  
10 P2  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
Q0  
CE  
2. Wafer and die for this part number is available which meets all elec-  
trical specifications. Please contact your local TI sales office or cus-  
tomer service for ordering information.  
U/D  
Q2  
Q3  
9
P3  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
FAST™ is a Trademark of Fairchild Semiconductor.  
1
Copyright © 2000, Texas Instruments Incorporated  

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