5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 计数器> CD54AC163F
CD54AC163F PDF预览

CD54AC163F

更新时间： 2024-11-20 00:00:55
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
12页 158K
描述
4-BIT SYNCHRONOUS BINARY COUNTERS

阅读下载

中文翻译

获取价格

CD54AC163F 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP16,.3针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.38计数方向：UP
系列：ACJESD-30 代码：R-GDIP-T16
长度：19.56 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：64000000 Hz最大I（ol）：0.012 A
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：3.3/5 V
传播延迟（tpd）：209 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.5 V
标称供电电压 (Vsup)：3 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：90 MHz
Base Number Matches：1

CD54AC163F 数据手册

 浏览型号CD54AC163F的Datasheet PDF文件第2页浏览型号CD54AC163F的Datasheet PDF文件第3页浏览型号CD54AC163F的Datasheet PDF文件第4页浏览型号CD54AC163F的Datasheet PDF文件第5页浏览型号CD54AC163F的Datasheet PDF文件第6页浏览型号CD54AC163F的Datasheet PDF文件第7页 
CD54AC163, CD74AC163  
4-BIT SYNCHRONOUS BINARY COUNTERS  
SCHS299 – APRIL 2000  
CD54AC163 . . . F PACKAGE  
CD74AC163 . . . E OR M PACKAGE  
(TOP VIEW)  
Internal Look-Ahead for Fast Counting  
Carry Output for n-Bit Cascading  
Synchronous Counting  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Synchronously Programmable  
Package Options Include Plastic  
Small-Outline (M), Standard Plastic (E) and  
Ceramic (F) DIPs  
Q
A
B
Q
B
C
Q
C
D
Q
D
description  
ENP  
GND  
ENT  
LOAD  
The CD54AC163 and CD74AC163 devices are  
4-bit binary counters. These synchronous,  
presettable counters feature an internal carry  
look-ahead for application in high-speed counting  
designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs  
change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating.  
This mode of operation eliminates the output counting spikes normally associated with synchronous  
(ripple-clock)counters. Abufferedclock(CLK)inputtriggersthefourflip-flopsontherising(positive-going)edge  
of the clock waveform.  
The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.  
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes  
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.  
The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low  
after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear  
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The  
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000  
(LLLL).  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.  
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a  
high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse  
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the  
level of CLK.  
These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that  
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of  
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
The CD54AC163 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The CD74AC163 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

下载PDF

与CD54AC163F相关器件

型号 品牌 获取价格 描述 数据表
CD54AC163F3A TI

获取价格

 		4-BIT SYNCHRONOUS BINARY COUNTERS
CD54AC163H GE

获取价格

 		Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS
CD54AC163HX GE

获取价格

 		Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS
CD54AC163M ETC

获取价格

 		Logic IC
CD54AC164 INTERSIL

获取价格

 		8-Bit Serial-In/Parallel-Out Shift Registers
CD54AC164 TI

获取价格

 		8-Bit Serial-In/Parallel-Out Shift Register
CD54AC164_07 TI

获取价格

 		8-Bit Serial-In/Parallel-Out Shift Register
CD54AC164_08 TI

获取价格

 		8-Bit Serial-In/Parallel-Out Shift Register
CD54AC1643A INTERSIL

获取价格

 		8-Bit Serial-In/Parallel-Out Shift Registers
CD54AC164E ETC

获取价格

 		Logic IC

与CD54AC163F相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证