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CD54AC163_14 PDF预览

CD54AC163_14

更新时间: 2024-11-25 02:58:43
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德州仪器 - TI /
页数 文件大小 规格书
12页 158K
描述
4-BIT SYNCHRONOUS BINARY COUNTERS

CD54AC163_14 数据手册

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CD54AC163, CD74AC163  
4-BIT SYNCHRONOUS BINARY COUNTERS  
SCHS299 – APRIL 2000  
CD54AC163 . . . F PACKAGE  
CD74AC163 . . . E OR M PACKAGE  
(TOP VIEW)  
Internal Look-Ahead for Fast Counting  
Carry Output for n-Bit Cascading  
Synchronous Counting  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Synchronously Programmable  
Package Options Include Plastic  
Small-Outline (M), Standard Plastic (E) and  
Ceramic (F) DIPs  
Q
A
B
Q
B
C
Q
C
D
Q
D
description  
ENP  
GND  
ENT  
LOAD  
The CD54AC163 and CD74AC163 devices are  
4-bit binary counters. These synchronous,  
presettable counters feature an internal carry  
look-ahead for application in high-speed counting  
designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs  
change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating.  
This mode of operation eliminates the output counting spikes normally associated with synchronous  
(ripple-clock)counters. Abufferedclock(CLK)inputtriggersthefourflip-flopsontherising(positive-going)edge  
of the clock waveform.  
The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.  
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes  
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.  
The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low  
after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear  
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The  
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000  
(LLLL).  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.  
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a  
high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse  
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the  
level of CLK.  
These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that  
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of  
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
The CD54AC163 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The CD74AC163 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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