CD4099BM

更新时间： 2024-11-22 22:54:19

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器锁存器逻辑集成电路光电二极管 PC
页数	文件大小	规格书
6页	139K
描述
8-Bit Addressable Latch

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数据手册

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CD4099BM 数据手册

February 1988

CD4099BM/CD4099BC 8-Bit Addressable Latch

General Description

Features

Wide supply voltage range

3.0V to 15V

0.45 V (typ.)

The CD4099B is an 8-bit addressable latch with three ad-

dress inputs (A0–A2), an active low enable input (E), active

high clear input (CL), a data input (D), and eight outputs

(Q0–Q7).

High noise immunity

Low power TTL

compatibility

fan out of 2 driving 74L

or 1 driving 74LS

Data is entered into a particular bit in the latch when that bit

is addressed by the address inputs and the enable (E) is

low. Data entry is inhibited when enable (E) is high.

Serial to parallel capability

Storage register capability

Random (addressable) data entry

When clear (CL) and enable (E) are high, all outputs are low.

When clear (CL) is high and enable (E) is low, the channel

demultiplexing occurs. The bit that is addressed has an ac-

tive output which follows the data input while all unad-

dressed bits are held low. When operating in the address-

Active high demultiplexing capability

Common active high clear

low), changing more than one

able latch mode (E

bit of the address could impose a transient wrong address.

Therefore, this should only be done while in the memory

low).

mode (E

high, CL

Connection Diagram

CD4099B

Dual-In-Line Package

Order Number CD4099B

TL/F/5984–1

Top View

Truth Table

Mode Selection

Unaddressed

Addressed

Latch

Mode

Latch

Follows Data

Holds Previous Data

Reset to ‘‘0’’

Addressable Latch

Memory

Holds Previous Data

Follows Data

Demultiplexer

Clear

Reset to ‘‘0’’

1995 National Semiconductor Corporation

TL/F/5984

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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CD4099BMJ	NSC	获取价格	4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16
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