Datasheet > CD4096BMS

CD4096BMS

更新时间： 2024-09-12 22:54:19

品牌	Logo	应用领域
英特矽尔 - INTERSIL		触发器栅
页数	文件大小	规格书
10页	103K
描述
CMOS Gated J-K Master-Slave Flip-Flops

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中文翻译

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数据手册

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CD4096BMS 数据手册

CD4095BMS

CD4096BMS

CMOS Gated J-K

Master-Slave Flip-Flops

December 1992

CD4095BMS

TOP VIEW

Features

Pinouts

• Set-Reset Capability

RESET

14 VDD

13 SET

12 CLOCK

11 K1

• High Voltage Types (20V Rating)

• CD4095BMS Non-Inverting J and K Inputs

• CD4096BMS Inverting and Non-Inverting J and K

Inputs

10 K2

• 16MHz Toggle Rate (Typ.) at VDD - VSS = 10V

• Gated Inputs

VSS

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

CD4096BMS

TOP VIEW

• Maximum Input Current of 1µA at 18V Over Full Pack-

RESET

14 VDD

13 SET

12 CLOCK

11 K1

age Temperature Range; 100nA at 18V and +25^oC

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

10 K2

- 2.5V at VDD = 15V

• Meets all requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

VSS

NC = NO CONNECTION

Applications

• Registers

Functional Diagrams

• Counters

CD4095BMS

SET

• Control Circuits

Description

CLOCK

CD4095BMS and CD4096BMS are J-K Master-Slave Flip-

Flops featuring separate AND gating of multiple J and K

inputs. The gated J-K inputs control transfer of information

into the master section during clocked operation. Information

on the J-K inputs is transferred to the Q and Q outputs on

the positive edge of the clock pulse. SET and RESET inputs

(active high) are provided for asynchronous operation.

VDD = 14

VSS = 7

NC = 1

RESET

SET

CD4096BMS

The CD4095BMS and CD4096BMS are supplied in these 14

lead outline packages:

Braze Seal DIP

Frit Seal DIP

H4Q

H1A

CLOCK

VDD = 14

VSS = 7

NC = 1

RESET

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3331

7-1094

12 3 4 5 6 7...10

中文翻译

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