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CD4069UBCSJ PDF预览

CD4069UBCSJ

更新时间: 2024-11-03 22:26:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 81K
描述
Inverter Circuits

CD4069UBCSJ 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:5.30 MM, EIAJ TYPE2, SOP-14
针数:14Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.38Is Samacsys:N
系列:4000/14000/40000JESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:10.2 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
湿度敏感等级:1功能数量:6
输入次数:1端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:5/15 VProp。Delay @ Nom-Sup:90 ns
传播延迟(tpd):90 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:2.1 mm
子类别:Gates最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

CD4069UBCSJ 数据手册

 浏览型号CD4069UBCSJ的Datasheet PDF文件第2页浏览型号CD4069UBCSJ的Datasheet PDF文件第3页浏览型号CD4069UBCSJ的Datasheet PDF文件第4页浏览型号CD4069UBCSJ的Datasheet PDF文件第5页浏览型号CD4069UBCSJ的Datasheet PDF文件第6页 
October 1987  
Revised January 1999  
CD4069UBC  
Inverter Circuits  
All inputs are protected from damage due to static dis-  
General Description  
charge by diode clamps to VDD and VSS  
.
The CD4069UB consists of six inverter circuits and is man-  
ufactured using complementary MOS (CMOS) to achieve  
wide power supply operating range, low power consump-  
tion, high noise immunity, and symmetric controlled rise  
and fall times.  
Features  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD typ.  
This device is intended for all general purpose inverter  
applications where the special characteristics of the  
MM74C901, MM74C907, and CD4049A Hex Inverter/Buff-  
ers are not required. In those applications requiring larger  
noise immunity the MM74C14 or MM74C914 Hex Schmitt  
Trigger is suggested.  
Low power TTL compatibility: Fan out of 2 driving 74L  
or 1 driving 74LS  
Equivalent to MM74C04  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4069UBCM  
CD4069UBCSJ  
CD4069UBCN  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.  
Connection Diagram  
Schematic Diagram  
Pin Assignments for SOIC and DIP  
© 1999 Fairchild Semiconductor Corporation  
DS005975.prf  
www.fairchildsemi.com  

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