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CD4066BCJ PDF预览

CD4066BCJ

更新时间: 2024-11-03 22:34:03
品牌 Logo 应用领域
美国国家半导体 - NSC 复用器开关复用器或开关信号电路光电二极管输出元件
页数 文件大小 规格书
8页 171K
描述
Quad Bilateral Switch

CD4066BCJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:CERDIP-14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.63
Is Samacsys:N模拟集成电路 - 其他类型:SPST
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
长度:19.43 mm正常位置:NO
信道数量:1功能数量:4
端子数量:14通态电阻匹配规范:5 Ω
最大通态电阻 (Ron):280 Ω最高工作温度:85 °C
最低工作温度:-40 °C输出:SEPARATE OUTPUT
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 V认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Multiplexer or Switches
标称供电电压 (Vsup):15 V表面贴装:NO
最长断开时间:25 ns最长接通时间:25 ns
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

CD4066BCJ 数据手册

 浏览型号CD4066BCJ的Datasheet PDF文件第2页浏览型号CD4066BCJ的Datasheet PDF文件第3页浏览型号CD4066BCJ的Datasheet PDF文件第4页浏览型号CD4066BCJ的Datasheet PDF文件第5页浏览型号CD4066BCJ的Datasheet PDF文件第6页浏览型号CD4066BCJ的Datasheet PDF文件第7页 
June 1992  
CD4066BM/CD4066BC Quad Bilateral Switch  
General Description  
Y
Extremely low ‘‘OFF’’  
switch leakage  
0.1 nA (typ.)  
The CD4066BM/CD4066BC is a quad bilateral switch in-  
tended for the transmission or multiplexing of analog or digi-  
tal signals. It is pin-for-pin compatible with CD4016BM/  
CD4016BC, but has a much lower ‘‘ON’’ resistance, and  
‘‘ON’’ resistance is relatively constant over the input-signal  
range.  
@
b
Extremely high control input impedance  
e
e
10V, T 25 C  
A
V
DD  
V
SS  
§
12  
Y
Y
10 X(typ.)  
b
0.9 MHz, R  
Low crosstalk  
50 dB (typ.)  
e
1 kX  
@
e
between switches  
f
is  
L
Y
Frequency response, switch ‘‘ON’’  
40 MHz (typ.)  
Features  
Y
Applications  
Y
Wide supply voltage range  
3V to 15V  
Analog signal switching/multiplexing  
Y
Y
High noise immunity  
0.45 V  
(typ.)  
PEAK  
DD  
Signal gating  
#
#
#
g
Wide range of digital and  
analog switching  
7.5 V  
Squelch control  
Chopper  
Y
Y
‘‘ON’’ resistance for 15V operation  
Matched ‘‘ON’’ resistance  
over 15V signal input  
80X  
Modulator/Demodulator  
#
e
DR  
ON  
5X (typ.)  
Commutating switch  
#
Digital signal switching/multiplexing  
Y
Y
Y
Y
Y
Y
‘‘ON’’ resistance flat over peak-to-peak signal range  
CMOS logic implementation  
High ‘‘ON’’/‘‘OFF’’  
output voltage ratio  
High degree linearity  
High degree linearity  
High degree linearity  
65 dB (typ.)  
Analog-to-digital/digital-to-analog conversion  
Digital control of frequency, impedance, phase, and an-  
alog-signal-gain  
@
e
e
0.1% distortion (typ.)  
f
10 kHz, R  
10 kX  
is  
L
Y
@
e
e
5V  
f
1 kHz, V  
,
is  
is  
p-p  
e
10V, R 10 kX  
L
b
e
V
V
SS  
DD  
Schematic and Connection Diagrams  
Order Number CD4066B  
Dual-In-Line Package  
TL/F/5665–1  
Top View  
C
1995 National Semiconductor Corporation  
TL/F/5665  
RRD-B30M105/Printed in U. S. A.  

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