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CD4060BCMX PDF预览

CD4060BCMX

更新时间: 2024-01-25 23:11:46
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
10页 350K
描述
Binary Counter, 4000/14000/40000 Series, Asynchronous, Negative Edge Triggered, 14-Bit, Up Direction, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16

CD4060BCMX 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:compliant风险等级:5.55
Samacsys Confidence:3Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/717466.1.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=717466
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=7174663D View:https://componentsearchengine.com/viewer/3D.php?partID=717466
Samacsys PartID:717466Samacsys Image:https://componentsearchengine.com/Images/9/CD4060BCMX.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/1/CD4060BCMX.jpgSamacsys Pin Count:16
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:16-Lead SOIC 0.150 Narrow_1Samacsys Released Date:2018-07-31 09:11:29
Is Samacsys:N计数方向:UP
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
长度:9.9 mm负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER工作模式:ASYNCHRONOUS
位数:14功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):1300 ns
座面最大高度:1.75 mm最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:NEGATIVE EDGE宽度:3.9 mm
最小 fmax:4 MHzBase Number Matches:1

CD4060BCMX 数据手册

 浏览型号CD4060BCMX的Datasheet PDF文件第2页浏览型号CD4060BCMX的Datasheet PDF文件第3页浏览型号CD4060BCMX的Datasheet PDF文件第4页浏览型号CD4060BCMX的Datasheet PDF文件第5页浏览型号CD4060BCMX的Datasheet PDF文件第6页浏览型号CD4060BCMX的Datasheet PDF文件第7页 
May 2007  
CD4040BC, 12-Stage Ripple Carry Binary Counters  
CD4060BC, 14-Stage Ripple Carry Binary Counters  
tm  
Features  
General Description  
Wide supply voltage range: 3.0V to 15V  
The CD4060BC is a 14-stage ripple carry binary counter,  
and the CD4040BC is a 12-stage ripple carry binary  
counter. The counters are advanced one count on the  
negative transition of each clock pulse. The counters are  
reset to the zero state by a logical “1” at the reset input  
independent of clock.  
High noise immunity: 0.45 V (Typ.)  
DD  
Low power TTL compatibility: Fan out of 2 driving 74L  
or 1 driving 74LS  
Medium speed operation: 8MHz typ. at V = 10V  
DD  
Schmitt trigger clock input  
Ordering Information  
Order  
Number  
Package  
Number  
Package Description  
CD4040BCM  
CD4060BCM  
CD4060BCN  
M16A  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.  
Connection Diagrams  
Pin Assignments for DIP and SOIC  
CD4040BC  
Pin Assignments for DIP and SOIC  
CD4060BC  
Top View  
Top View  
©1987 Fairchild Semiconductor Corporation  
CD4040BC, DCD4060BC Rev. 1.5  
www.fairchildsemi.com  

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