生命周期: | Active | 零件包装代码: | DIP |
包装说明: | DIP, DIP16,.3 | 针数: | 16 |
Reach Compliance Code: | not_compliant | ECCN代码: | EAR99 |
HTS代码: | 8542.39.00.01 | Factory Lead Time: | 1 week |
风险等级: | 5.15 | 模拟集成电路 - 其他类型: | SINGLE-ENDED MULTIPLEXER |
标称带宽: | 30 MHz | 最大输入电压: | 20.5 V |
最小输入电压: | -0.5 V | JESD-30 代码: | R-GDIP-T16 |
长度: | 19.56 mm | 标称负供电电压 (Vsup): | -5 V |
正常位置: | NC | 信道数量: | 2 |
功能数量: | 3 | 端子数量: | 16 |
标称断态隔离度: | 40 dB | 通态电阻匹配规范: | 15 Ω |
最大通态电阻 (Ron): | 1050 Ω | 最高工作温度: | 125 °C |
最低工作温度: | -55 °C | 输出: | SEPARATE OUTPUT |
封装主体材料: | CERAMIC, GLASS-SEALED | 封装代码: | DIP |
封装等效代码: | DIP16,.3 | 封装形状: | RECTANGULAR |
封装形式: | IN-LINE | 峰值回流温度(摄氏度): | NOT SPECIFIED |
电源: | 5/15 V | 认证状态: | Not Qualified |
筛选级别: | MIL-STD-883 | 座面最大高度: | 5.08 mm |
最大信号电流: | 0.01 A | 子类别: | Multiplexer or Switches |
最大供电电流 (Isup): | 3 mA | 最大供电电压 (Vsup): | 20 V |
最小供电电压 (Vsup): | 3 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | NO | 最长断开时间: | 720 ns |
最长接通时间: | 720 ns | 切换: | BREAK-BEFORE-MAKE |
技术: | CMOS | 温度等级: | MILITARY |
端子形式: | THROUGH-HOLE | 端子节距: | 2.54 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | NOT SPECIFIED |
宽度: | 7.62 mm | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
CD4053BF3 | RENESAS |
获取价格 |
TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, CDIP16 | |
CD4053BF3A | TI |
获取价格 |
CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion | |
CD4053BF3AS2283 | TI |
获取价格 |
CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion | |
CD4053BFMS | RENESAS |
获取价格 |
TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, CDIP16, FRIT SEALED, DIP-16 | |
CD4053BH | TI |
获取价格 |
4000/14000/40000 SERIES, HEX 1-BIT DRIVER, TRUE OUTPUT, UUC16, DIE-16 | |
CD4053BKMS | RENESAS |
获取价格 |
Single-Ended Multiplexer, 3 Func, 2 Channel, CMOS, CDFP16 | |
CD4053BKMSR | ETC |
获取价格 |
2-Channel Analog Multiplexer | |
CD4053BM | NSC |
获取价格 |
Single 8(4/2)-Channel Analog Multiplexer/Demultiplexer | |
CD4053BM | TI |
获取价格 |
CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion | |
CD4053BM | HARRIS |
获取价格 |
CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion |