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CD4052BC PDF预览

CD4052BC

更新时间: 2024-02-12 01:39:39
品牌 Logo 应用领域
美国国家半导体 - NSC 解复用器
页数 文件大小 规格书
10页 191K
描述
Single 8(4/2)-Channel Analog Multiplexer/Demultiplexer

CD4052BC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.67模拟集成电路 - 其他类型:DIFFERENTIAL MULTIPLEXER
标称带宽:25 MHz最大输入电压:20.5 V
最小输入电压:-0.5 VJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
湿度敏感等级:1标称负供电电压 (Vsup):-5 V
正常位置:NC信道数量:4
功能数量:1端子数量:16
标称断态隔离度:40 dB通态电阻匹配规范:15 Ω
最大通态电阻 (Ron):1050 Ω最高工作温度:125 °C
最低工作温度:-55 °C输出:SEPARATE OUTPUT
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5/15 V认证状态:Not Qualified
座面最大高度:1.2 mm最大信号电流:0.01 A
子类别:Multiplexer or Switches最大供电电流 (Isup):3 mA
最大供电电压 (Vsup):20 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
最长断开时间:720 ns最长接通时间:720 ns
切换:BREAK-BEFORE-MAKE技术:CMOS
温度等级:MILITARY端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

CD4052BC 数据手册

 浏览型号CD4052BC的Datasheet PDF文件第2页浏览型号CD4052BC的Datasheet PDF文件第3页浏览型号CD4052BC的Datasheet PDF文件第4页浏览型号CD4052BC的Datasheet PDF文件第5页浏览型号CD4052BC的Datasheet PDF文件第6页浏览型号CD4052BC的Datasheet PDF文件第7页 
October 1989  
CD4051BM/CD4051BC Single 8-Channel Analog  
Multiplexer/Demultiplexer  
CD4052BM/CD4052BC Dual 4-Channel Analog  
Multiplexer/Demultiplexer  
CD4053BM/CD4053BC Triple 2-Channel Analog  
Multiplexer/Demultiplexer  
General Description  
These analog multiplexers/demultiplexers are digitally con-  
trolled analog switches having low ‘‘ON’’ impedance and  
very low ‘‘OFF’’ leakage currents. Control of analog signals  
an inhibit input. Each control input selects one of a pair of  
channels which are connected in a single-pole double-throw  
configuration.  
up to 15V  
p-p  
3–15V. For example, if V  
can be achieved by digital signal amplitudes of  
eb  
e
e
0V and V  
EE  
5V, V  
SS  
5V,  
DD  
Features  
Y
b
a
analog signals from 5V to 5V can be controlled by digi-  
tal inputs of 05V. The multiplexer circuits dissipate ex-  
Wide range of digital and analog signal levels: digital  
3–15V, analog to 15V  
p-p  
b
tremely low quiescent power over the full V  
DD  
V
and  
SS  
supply voltage ranges, independent of the logic  
Y
Y
Y
Low ‘‘ON’’ resistance: 80X (typ.) over entire 15V  
sig-  
p-p  
b
V
V
EE  
DD  
b
High ‘‘OFF’’ resistance: channel leakage of  
e
V
EE  
nal-input range for V  
15V  
DD  
state of the control signals. When a logical ‘‘1’’ is present at  
the inhibit input terminal all channels are ‘‘OFF’’.  
g
10 pA  
b
Logic level conversion for digital addressing signals of  
e
EE  
(typ.) at V  
V
10V  
DD  
CD4051BM/CD4051BC is a single 8-channel multiplexer  
having three binary control inputs. A, B, and C, and an inhibit  
input. The three binary signals select 1 of 8 channels to be  
turned ‘‘ON’’ and connect the input to the output.  
b
e
3–15V) to switch analog signals to  
3–15V (V  
DD  
V
SS  
b
e
15 V  
(V  
DD  
V
EE  
15V)  
p-p  
Y
Y
e
Matched switch characteristics: DR  
ON  
5X (typ.) for  
CD4052BM/CD4052BC is a differential 4-channel multiplex-  
er having two binary control inputs, A and B, and an inhibit  
input. The two binary input signals select 1 or 4 pairs of  
channels to be turned on and connect the differential ana-  
log inputs to the differential outputs.  
b
e
V
V
EE  
15V  
Very low quiescent power dissipation under all digital-  
control input and supply conditions: mW (typ.) at  
DD  
1
b
e
b
Binary address decoding on chip  
e
V
V
V
DD  
V
EE  
10V  
DD  
SS  
Y
CD4053BM/CD4053BC is a triple 2-channel multiplexer  
having three separate digital control inputs, A, B, and C, and  
Connection Diagrams  
Dual-In-Line Packages  
CD4052BM/CD4052BC  
CD4051BM/CD4051BC  
CD4053BM/CD4053BC  
TL/F/5662–1  
Order Number CD4051B, CD4052B, or CD4053B  
C
1995 National Semiconductor Corporation  
TL/F/5662  
RRD-B30M105/Printed in U. S. A.  

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