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CD4050BDWR PDF预览

CD4050BDWR

更新时间: 2024-02-15 20:58:35
品牌 Logo 应用领域
德州仪器 - TI 转换器逻辑集成电路光电二极管
页数 文件大小 规格书
18页 440K
描述
CMOS HEX BUFFERS/CONVERTERS

CD4050BDWR 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.09系列:4000/14000/40000
JESD-30 代码:R-PDSO-G16长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:BUFFER
功能数量:6输入次数:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:5/15 V
Prop。Delay @ Nom-Sup:140 ns传播延迟(tpd):140 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):5 V
标称供电电压 (Vsup):10 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

CD4050BDWR 数据手册

 浏览型号CD4050BDWR的Datasheet PDF文件第2页浏览型号CD4050BDWR的Datasheet PDF文件第3页浏览型号CD4050BDWR的Datasheet PDF文件第4页浏览型号CD4050BDWR的Datasheet PDF文件第5页浏览型号CD4050BDWR的Datasheet PDF文件第6页浏览型号CD4050BDWR的Datasheet PDF文件第7页 
CD4049UB, CD4050B  
August 1998 - Revised May 2004  
Data sheet acquired from Harris Semiconductor  
SCHS046I  
CMOS Hex Buffer/Converters  
Applications  
The CD4049UB and CD4050B devices are inverting and  
non-inverting hex buffers, respectively, and feature logic-  
• CMOS to DTL/TTL Hex Converter  
• CMOS Current “Sink” or “Source” Driver  
• CMOS High-To-Low Logic Level Converter  
level conversion using only one supply voltage (V ). The  
CC  
supply  
input-signal high level (V ) can exceed the V  
IH  
CC  
voltage when these devices are used for logic-level  
conversions. These devices are intended for use as CMOS  
to DTL/TTL converters and can drive directly two DTL/TTL  
[ /Title  
(CD40  
49UB,  
CD405  
0B)  
/Sub-  
ject  
(CMO  
S Hex  
Buffer/  
Con-  
verters)  
/Autho  
r ()  
/Key-  
words  
(Harris  
Semi-  
con-  
ductor,  
CD400  
0,  
metal  
gate,  
Ordering Information  
TEMP.  
o
loads. (V  
= 5V, V 0.4V, and I  
3.3mA.)  
PART NUMBER  
CD4049UBF3A  
CD4050BF3A  
CD4049UBD  
RANGE ( C)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOP  
CC  
OL  
OL  
The CD4049UB and CD4050B are designated as  
replacements for CD4009UB and CD4010B, respectively.  
Because the CD4049UB and CD4050B require only one  
power supply, they are preferred over the CD4009UB and  
CD4010B and should be used in place of the CD4009UB  
and CD4010B in all inverter, current driver, or logic-level  
conversion applications. In these applications the  
CD4049UB and CD4050B are pin compatible with the  
CD4009UB and CD4010B respectively, and can be  
substituted for these devices in existing as well as in new  
designs. Terminal No. 16 is not connected internally on the  
CD4049UB or CD4050B, therefore, connection to this  
terminal is of no consequence to circuit operation. For  
applications not requiring high sink-current or voltage  
conversion, the CD4069UB Hex Inverter is recommended.  
CD4049UBDR  
CD4049UBDT  
CD4049UBDW  
CD4049UBDWR  
CD4049UBE  
CD4049UBNSR  
CD4049UBPW  
CD4049UBPWR  
CD4050BD  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOP  
Features  
CD4050BDR  
• CD4049UB Inverting  
• CD4050B Non-Inverting  
CD4050UBDT  
CD4050BDW  
CD4050BDWR  
CD4050BE  
• High Sink Current for Driving 2 TTL Loads  
• High-To-Low Level Logic Conversion  
• 100% Tested for Quiescent Current at 20V  
• Maximum Input Current of 1µA at 18V Over Full Package  
o
Temperature Range; 100nA at 18V and 25 C  
CD4050NSR  
5V, 10V and 15V Parametric Ratings  
CD4050BPW  
CD4050BPWR  
16 Ld TSSOP  
16 Ld TSSOP  
CMOS  
NOTE: When ordering, use the entire part number. The suffix R denotes tape  
and reel. The suffix T denotes a small-quantity reel of 250.  
Pinouts  
CD4049UB (PDIP, CERDIP, SOIC, SOP, TSSOP)  
CD4050B (PDIP, CERDIP, SOIC, SOP)  
TOP VIEW  
TOP VIEW  
V
1
2
3
4
5
6
7
8
16 NC  
15 L = F  
14 F  
V
1
2
3
4
5
6
7
8
16 NC  
15 L = F  
14 F  
CC  
CC  
G = A  
A
G = A  
A
H = B  
B
13 NC  
12 K = E  
11 E  
H = B  
B
13 NC  
12 K = E  
11 E  
I = C  
C
I = C  
C
10 J = D  
10 J = D  
9
D
V
9
D
V
SS  
SS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Copyright © 2004, Texas Instruments Incorporated  
1

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