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CD4049UBMN PDF预览

CD4049UBMN

更新时间: 2024-11-03 23:40:27
品牌 Logo 应用领域
美国国家半导体 - NSC 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 132K
描述
Hex Inverter

CD4049UBMN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.04
其他特性:CMOS-TTL LEVEL TRANSLATOR系列:4000/14000/40000
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:19.34 mm负载电容(CL):50 pF
逻辑集成电路类型:INVERTER功能数量:6
输入次数:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/15 VProp。Delay @ Nom-Sup:120 ns
传播延迟(tpd):65 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

CD4049UBMN 数据手册

 浏览型号CD4049UBMN的Datasheet PDF文件第2页浏览型号CD4049UBMN的Datasheet PDF文件第3页浏览型号CD4049UBMN的Datasheet PDF文件第4页浏览型号CD4049UBMN的Datasheet PDF文件第5页浏览型号CD4049UBMN的Datasheet PDF文件第6页 
March 1988  
CD4049UBM/CD4049UBC Hex Inverting Buffer  
CD4050BM/CD4050BC Hex Non-Inverting Buffer  
General Description  
These hex buffers are monolithic complementary MOS  
(CMOS) integrated circuits constructed with N- and P-chan-  
nel enhancement mode transistors. These devices feature  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
Y
Direct drive to 2 TTL loads at 5.0V over full tempera-  
ture range  
Y
Y
logic level conversion using only one supply voltage (V ).  
DD  
High source and sink current capability  
Special input protection permits input voltages greater  
than V  
The input signal high level (V ) can exceed the V  
IH  
supply  
DD  
voltage when these devices are used for logic level conver-  
sions. These devices are intended for use as hex buffers,  
CMOS to DTL/TTL converters, or as CMOS current drivers,  
DD  
Applications  
Y
e
loads over the full operating temperature range.  
and at V  
5.0V, they can drive directly two DTL/TTL  
DD  
CMOS hex inverter/buffer  
Y
CMOS to DTL/TTL hex converter  
Y
CMOS current ‘‘sink’’ or ‘‘source’’ driver  
Y
CMOS high-to-low logic level converter  
Connection Diagrams  
CD4049UBM/CD4049UBC  
Dual-In-Line Package  
CD4050BM/CD4050BC  
Dual-In-Line Package  
TL/F/5971–1  
TL/F/5971–2  
Top View  
Top View  
Order Number CD4049UB or CD4049B  
Order Number CD4050UB or CD4050B  
C
1995 National Semiconductor Corporation  
TL/F/5971  
RRD-B30M105/Printed in U. S. A.  

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