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CD4044

更新时间: 2024-11-13 22:54:19
品牌 Logo 应用领域
美国国家半导体 - NSC 锁存器
页数 文件大小 规格书
6页 138K
描述
Quad TRI-STATE NOR(NAND) R/S Latches

CD4044 数据手册

 浏览型号CD4044的Datasheet PDF文件第2页浏览型号CD4044的Datasheet PDF文件第3页浏览型号CD4044的Datasheet PDF文件第4页浏览型号CD4044的Datasheet PDF文件第5页浏览型号CD4044的Datasheet PDF文件第6页 
February 1988  
CD4043BM/CD4043BC Quad TRI-STATE  
NOR R/S Latches  
É
CD4044BM/CD4044BC Quad TRI-STATE  
NAND R/S Latches  
General Description  
Features  
Y
Wide supply voltage range  
Low power  
3V to 15V  
CD4043BM/CD4043BC are quad cross-couple TRI-STATE  
CMOS NOR latches, and CD4044BM/CD4044BC are quad  
cross-couple TRI-STATE CMOS NAND latches. Each latch  
has a separate Q output and individual SET and RESET  
inputs. There is a common TRI-STATE ENABLE input for all  
four latches. A logic ‘‘1’’ on the ENABLE input connects the  
latch states to the Q outputs. A logic ‘‘0’’ on the ENABLE  
input disconnects the latch states from the Q outputs result-  
Y
Y
Y
Y
Y
100 nW (typ.)  
High noise immunity  
0.45 V  
(typ.)  
DD  
Separate SET and RESET inputs for each latch  
NOR and NAND configuration  
TRI-STATE output with common output enable  
Applications  
Y
ing in an open circuit condition on the Q output. The  
TRI-STATE feature allows common bussing of the outputs.  
Multiple bus storage  
Y
Strobed register  
Y
Four bits of independent storage with output enable  
General digital logic  
Y
Connection Diagrams  
CD4043BM/CD4043BC  
Dual-In-Line and Flat Packages  
CD4044BM/CD4044BC  
Dual-In-Line and Flat Packages  
TL/F/5967–4  
TL/F/5967–3  
Top View  
Top View  
Order Number CD4043B or CD4044B  
Truth Table  
OC Ð TRI-STATE  
NC Ð No change  
CD4043BM/CD4043BC  
CD4044BM/CD4044BC  
X
Ð Don’t care  
Ð Dominated by S 1 input  
S
R
E
Q
S
R
E
Q
e
D
X
0
1
0
1
X
0
0
1
1
0
1
1
1
1
OC  
NC  
1
X
1
0
1
0
X
1
1
0
0
0
1
1
1
1
OC  
NC  
1
e
DD Ð Dominated by R 0 input  
0
0
D
DD  
C
1995 National Semiconductor Corporation  
TL/F/5967  
RRD-B30M105/Printed in U. S. A.  

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