Datasheet > CD4043BMS

CD4043BMS

更新时间： 2024-09-25 22:54:19

品牌	Logo	应用领域
英特矽尔 - INTERSIL		逻辑集成电路
页数	文件大小	规格书
10页	112K
描述
CMOS Quad Clocked “D” Latch

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中文翻译

获取价格

数据手册

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CD4043BMS 数据手册

CD4043BMS

CD4044BMS

CMOS Quad 3 State R/S Latches

December 1992

Features

Pinout

• High Voltage Types (20V Rating)

CD4043BMS

TOP VIEW

• Quad NOR R/S Latch- CD4043BMS

• Quad NAND R/S Latch - CD4044BMS

• 3 State Outputs with Common Output ENABLE

• Separate SET and RESET Inputs for Each Latch

• NOR and NAND Conﬁguration

16 VDD

15 R4

14 S4

13 NC

12 S3

11 R3

10 Q3

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

ENABLE

• Maximum Input Current of 1µa at 18V Over Full Pack-

VSS

age-Temperature Range;

- 100nA at 18V and 25^oC

NC = NO CONNECTION

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

CD4044BMS

TOP VIEW

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of ‘B’

Series CMOS Devices”

16 VDD

15 S4

14 R4

13 Q1

12 R3

11 S3

10 Q3

Applications

• Holding Register in Multi-Register System

• Four Bits of Independent Storage with Output ENABLE

• Strobed Register

ENABLE

• General Digital Logic

VSS

• CD4043BMS for Positive Logic Systems

• CD4044BMS for Negative Logic Systems

NC = NO CONNECTION

Description

CD4043BMS types are quad cross-coupled 3-state CMOS NOR

latches and the CD4044BMS types are quad cross-coupled 3-

state CMOS NAND latches. Each latch has a separate Q output

and individual SET and RESET inputs. The Q outputs are con-

trolled by a common ENABLE input. A logic “1” or high on the

ENABLE input connects the latch states to the Q outputs. A logic

“0” or low on the ENABLE input disconnects the latch states from

the Q outputs, results in an open circuit feature allows common

busing of the outputs.

The CD4043BMS and CD4044BMS are supplied in these 16-

lead outline packages:

Braze Seal DIP

Frit Seal DIP

*H4T

*H1C

†H4T

†HIE

Ceramic Flatpack

*CD4043B Only

*H3X †H6W

†CD4044B Only

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3311

7-876

12 3 4 5 6 7...10

中文翻译

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与CD4043BMS相关器件

型号	品牌	获取价格	描述	数据表
CD4043BMSH	INTERSIL	获取价格	CMOS Quad Clocked “D” Latch
CD4043BMW	NSC	获取价格	IC,LATCH,QUAD,1-BIT,CMOS,FP,16PIN,CERAMIC
CD4043BNSR	TI	获取价格	CMOS QUAD 3-STATE R/S LATCHES
CD4043BNSRG4	TI	获取价格	4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, PDSO16, GREEN, PLAST
CD4043BPW	TI	获取价格	CMOS QUAD 3-STATE R/S LATCHES
CD4043BPWG4	TI	获取价格	4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, PDSO16, GREEN, PLAST
CD4043BPWR	TI	获取价格	CMOS QUAD 3-STATE R/S LATCHES
CD4043BPWRE4	TI	获取价格	CMOS Quad NOR R/S Latch with 3-State Outputs 16-TSSOP -55 to 125
CD4043BPWRG4	TI	获取价格	4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, PDSO16, GREEN, PLAST
CD4043CJ/A+	ETC	获取价格	S-R-Type Latch

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