Datasheet > CD4035BKMSR

CD4035BKMSR

更新时间： 2024-09-25 08:52:35

品牌	Logo	应用领域
瑞萨 - RENESAS		输出元件
页数	文件大小	规格书
10页	118K
描述
4000/14000/40000 SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, CONFIGURABLE OUTPUT, CDFP16

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CD4035BKMSR 数据手册

CD4035BMS

CMOS 4 -Stage Parallel

In/Parallel Out Shift Register

December 1992

Features

Description

• J - K Serial Inputs and True/Complement Outputs

• High Voltage Type (20V Rating)

CD4035BMS is a four stage clocked signal serial register

with provision for synchronous PARALLEL inputs to each

stage and SERIAL inputs to the ﬁrst stage via JK logic. Reg-

ister stages 2, 3, and 4 are coupled in a serial D ﬂip-ﬂop con-

ﬁguration when the register is in the serial mode

(PARALLEL/SERIAL control low).

• 4-Stage Clocked Shift Operation

• Synchronous Parallel Entry on All 4 Stages

• JK Inputs on First Stage

Parallel entry into each register stage is permitted when the

PARALLEL/SERIAL control is high.

• Asynchronous True/Complement Control on All Out-

puts

In the parallel or serial mode information is transferred on

positive clock transitions.

• Static Flip-Flop Operation; Master-Slave Conﬁgura-

tion

When the TRUE/COMPLEMENT control is high, the true

contents of the register are available at the output terminals.

When the TRUE/COMPLEMENT control is low, the outputs

are the complements of the data in the register. The TRUE/

COMPLEMENT control functions asynchronously with

respect to the CLOCK signal.

• Buffered Inputs and Outputs

• High Speed Operation 12MHz (Typ) at VDD = 10V

• 100% Tested for Quiescent Current at 20V

• Standardized, Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

JK input logic is provided on the ﬁrst stage SERIAL input to

minimize logic requirements particularly in counting and

sequence-generation applications. With JK inputs connected

together, the ﬁrst stage becomes a D ﬂip-ﬂop. An asynchro-

nous common, RESET is also provided.

• Meets All Requirements of JEDEC Tentative Standard

Number 13A, “Standard Speciﬁcations for Description

of ‘B’ Series CMOS Devices”

Applications

The CD4035BMS series type is supplied in these 16 lead

outline packages

• Counters, Registers

Braze Seal DIP

Frit Seal DIP

H4T

H1F

- Arithmetic-Unit Registers

- Shift Left/Shift Right Registers

- Serial-to-Parallel/Parallel-to-Serial Conversions

Ceramic Flatpack H6W

• Sequence Generation

• Control Circuits

• Code Conversion

Functional Diagram

Pinout

FIRST STAGE TRUTH TABLE

CD4035BMS

TOP VIEW

PARALLEL IN

tn-1 (INPUT)

(OUTPUT)

Qn-1

Q1/Q1

16 VDD

15 Q2/Q2

14 Q3/Q3

13 Q4/Q4

12 PI-4

SER

TRUE/

COMP.

CLK

P/S

4-STAGE REGISTER

Qn-1

Toggle

Mode

T/C

RESET

CLOCK

P/S

RESET

11 PI-3

Qn-1

VDD = 16

VSS = 8

10 PI-2

Q1/Q1 Q2/Q2 Q3/Q3 Q4/Q4

T/C OUT

PI-1

VSS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3308

7-851

12 3 4 5 6 7...10

中文翻译

下载PDF

与CD4035BKMSR相关器件

型号	品牌	获取价格	描述	数据表
CD4035BM	TI	获取价格	Parallel In/Parallel Out Shift Refister
CD4035BM	NSC	获取价格	4-Bit Parallel-In/Parallel-Out Shift Register
CD4035BM96	TI	获取价格	Parallel In/Parallel Out Shift Refister
CD4035BM96E4	TI	获取价格	Parallel In/Parallel Out Shift Refister
CD4035BM96G4	TI	获取价格	Parallel In/Parallel Out Shift Refister
CD4035BMD	TI	获取价格	IC,SHIFT REGISTER,CMOS,DIP,16PIN,CERAMIC
CD4035BMD	NSC	获取价格	暂无描述
CD4035BMD/883B	TI	获取价格	IC,SHIFT REGISTER,CMOS,DIP,16PIN,CERAMIC
CD4035BME4	TI	获取价格	Parallel In/Parallel Out Shift Refister
CD4035BMG4	TI	获取价格	Parallel In/Parallel Out Shift Refister

与CD4035BKMSR相关文章

SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

7
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

12
摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

80
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

71

产品中心

服务支持

精选活动

关于我们

帮助中心

CD4035BKMSR

CD4035BKMSR 数据手册

与CD4035BKMSR相关器件

与CD4035BKMSR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CD4035BKMSR

CD4035BKMSR 数据手册

与CD4035BKMSR相关器件

与CD4035BKMSR相关文章

您还可以找

您在本页遇到什么问题？