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CD4035BDMSR PDF预览

CD4035BDMSR

更新时间： 2024-09-24 14:50:31
品牌 Logo 应用领域
瑞萨 - RENESAS 输出元件逻辑集成电路触发器
页数 文件大小 规格书
10页 118K
描述
4000/14000/40000 SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, CONFIGURABLE OUTPUT, CDIP16, BRAZE SEALED, DIP-16

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CD4035BDMSR 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.15
Is Samacsys：N计数方向：RIGHT
系列：4000/14000/40000JESD-30 代码：R-CDIP-T16
JESD-609代码：e0长度：19.05 mm
逻辑集成电路类型：PARALLEL IN PARALLEL OUT最大频率@ Nom-Sup：2000000 Hz
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：CONFIGURABLE
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 V传播延迟（tpd）：675 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class V
座面最大高度：5.08 mm子类别：Shift Registers
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED总剂量：100k Rad(Si) V
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：1.48 MHzBase Number Matches：1

CD4035BDMSR 数据手册

 浏览型号CD4035BDMSR的Datasheet PDF文件第2页浏览型号CD4035BDMSR的Datasheet PDF文件第3页浏览型号CD4035BDMSR的Datasheet PDF文件第4页浏览型号CD4035BDMSR的Datasheet PDF文件第5页浏览型号CD4035BDMSR的Datasheet PDF文件第6页浏览型号CD4035BDMSR的Datasheet PDF文件第7页 
CD4035BMS  
CMOS 4 -Stage Parallel  
In/Parallel Out Shift Register  
December 1992  
Features  
Description  
• J - K Serial Inputs and True/Complement Outputs  
• High Voltage Type (20V Rating)  
CD4035BMS is a four stage clocked signal serial register  
with provision for synchronous PARALLEL inputs to each  
stage and SERIAL inputs to the first stage via JK logic. Reg-  
ister stages 2, 3, and 4 are coupled in a serial D flip-flop con-  
figuration when the register is in the serial mode  
(PARALLEL/SERIAL control low).  
• 4-Stage Clocked Shift Operation  
• Synchronous Parallel Entry on All 4 Stages  
• JK Inputs on First Stage  
Parallel entry into each register stage is permitted when the  
PARALLEL/SERIAL control is high.  
• Asynchronous True/Complement Control on All Out-  
puts  
In the parallel or serial mode information is transferred on  
positive clock transitions.  
• Static Flip-Flop Operation; Master-Slave Configura-  
tion  
When the TRUE/COMPLEMENT control is high, the true  
contents of the register are available at the output terminals.  
When the TRUE/COMPLEMENT control is low, the outputs  
are the complements of the data in the register. The TRUE/  
COMPLEMENT control functions asynchronously with  
respect to the CLOCK signal.  
• Buffered Inputs and Outputs  
• High Speed Operation 12MHz (Typ) at VDD = 10V  
• 100% Tested for Quiescent Current at 20V  
• Standardized, Symmetrical Output Characteristics  
• 5V, 10V and 15V Parametric Ratings  
JK input logic is provided on the first stage SERIAL input to  
minimize logic requirements particularly in counting and  
sequence-generation applications. With JK inputs connected  
together, the first stage becomes a D flip-flop. An asynchro-  
nous common, RESET is also provided.  
• Meets All Requirements of JEDEC Tentative Standard  
Number 13A, “Standard Specifications for Description  
of ‘B’ Series CMOS Devices”  
Applications  
The CD4035BMS series type is supplied in these 16 lead  
outline packages  
• Counters, Registers  
Braze Seal DIP  
Frit Seal DIP  
H4T  
H1F  
- Arithmetic-Unit Registers  
- Shift Left/Shift Right Registers  
- Serial-to-Parallel/Parallel-to-Serial Conversions  
Ceramic Flatpack H6W  
• Sequence Generation  
• Control Circuits  
• Code Conversion  
Functional Diagram  
Pinout  
FIRST STAGE TRUTH TABLE  
CD4035BMS  
TOP VIEW  
PARALLEL IN  
tn  
tn-1 (INPUT)  
(OUTPUT)  
1
2
3
4
9
10  
11  
12  
CL  
J
0
1
X
1
K
X
X
0
R
0
0
0
0
Qn-1  
Qn  
0
4
3
6
7
2
5
Q1/Q1  
1
2
3
4
5
6
7
8
16 VDD  
15 Q2/Q2  
14 Q3/Q3  
13 Q4/Q4  
12 PI-4  
J
0
0
SER  
IN  
TRUE/  
COMP.  
K
1
CLK  
P/S  
K
J
4-STAGE REGISTER  
1
0
0
Qn-1  
Qn-1  
Toggle  
Mode  
T/C  
RESET  
CLOCK  
P/S  
RESET  
11 PI-3  
1
15  
14  
13  
X
X
X
1
X
X
0
0
1
1
Qn-1  
X
1
Qn-1  
0
VDD = 16  
VSS = 8  
10 PI-2  
Q1/Q1 Q2/Q2 Q3/Q3 Q4/Q4  
T/C OUT  
9
PI-1  
VSS  
X
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3308  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-851  
1234567...10

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