February 1988
CD4035BM/CD4035BC
4-Bit Parallel-In/Parallel-Out Shift Register
General Description
Features
Y
Wide supply voltage range
3.0V to 15V
0.45 V (typ.)
The CD4035B 4-bit parallel-in/parallel-out shift register is a
monolithic complementary MOS (CMOS) integrated circuit
constructed with P- and N-channel enhancement mode
transistors. This shift register is a 4-stage clocked serial reg-
ister having provisions for synchronous parallel inputs to
each stage and serial inputs to the first stage via JK logic.
Register stages 2, 3, and 4 are coupled in a serial ‘‘D’’ flip-
flop configuration when the register is in the serial mode
(parallel/serial control low).
Y
High noise immunity
DD
Y
Low power TTL
compatibility
Fan out of 2 driving 74L
or 1 driving 74LS
Y
4-stage clocked operation
Y
Synchronous parallel entry on all 4 stages
JK inputs on first stage
Y
Y
Y
Y
Y
Y
Y
Asynchronous true/complement control on all outputs
Reset control
Parallel entry via the ‘‘D’’ line of each register stage is per-
mitted only when the parallel/serial control is ‘‘high’’.
Static flip-flop operation; master/slave configuration
Buffered outputs
In the parallel or serial mode, information is transferred on
positive clock transitions.
Low power dissipation
High speed
5 mW (typ.) (ceramic)
to 5 MHz
When the true/complement control is ‘‘high’’, the true con-
tents of the register are available at the output terminals.
When the true/complement control is ‘‘low’’, the outputs are
the complements of the data in the register. The true/com-
plement control functions asynchronously with respect to
the clock signal.
Applications
Y
Y
Y
Y
Y
Automotive
Alarm systems
Industrial controls
Remote metering
Computers
Y
Data terminals
Y
Instrumentation
Y
Medical electronics
JK input logic is provided on the first stage serial input to
minimize logic requirements particularly in counting and se-
quence-generation applications. With JK inputs connected
together, the first stage becomes a ‘‘D’’ flip-flop. An asyn-
chronous common reset is also provided.
Logic Diagram
TL/F/5964–1
e
e
e
e
e
P/S
T/C
*TG
0
1
serial mode
true outputs
Input to output is:
a) A bidirectional low impedance when control input 1 is low and control input 2 is high.
b) An open circuit when control input 1 is high and control input 2 is low.
transmission gate
TL/F/5964–2
C
1995 National Semiconductor Corporation
TL/F/5964
RRD-B30M105/Printed in U. S. A.