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CD4029BM PDF预览

CD4029BM

更新时间: 2024-11-11 22:54:19
品牌 Logo 应用领域
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页数 文件大小 规格书
8页 166K
描述
Presettable Binary/Decade Up/Down Counter

CD4029BM 数据手册

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February 1988  
CD4029BM/CD4029BC Presettable  
Binary/Decade Up/Down Counter  
General Description  
The CD4029BM/CD4029BC is  
a
presettable up/down  
count in the ‘‘up’’ mode or the minimum count in the ‘‘down’’  
mode provided the carry input is at logical ‘‘0’’ state.  
counter which counts in either binary or decade mode de-  
pending on the voltage level applied at binary/decade input.  
When binary/decade is at logical ‘‘1’’, the counter counts in  
binary, otherwise it counts in decade. Similarly, the counter  
counts up when the up/down input is at logical ‘‘1’’ and vice  
versa.  
All inputs are protected against static discharge by diode  
clamps to both V  
and V  
.
SS  
DD  
Features  
Y
Wide supply voltage range  
High noise immunity  
Low power  
3V to 15V  
0.45 V (typ.)  
A logical ‘‘1’’ preset enable signal allows information at the  
‘‘jam’’ inputs to preset the counter to any state asynchro-  
nously with the clock. The counter is advanced one count at  
the positive-going edge of the clock if the carry in and pre-  
set enable inputs are at logical ‘‘0’’. Advancement is inhibit-  
ed when either or both of these two inputs is at logical ‘‘1’’.  
The carry out signal is normally at logical ‘‘1’’ state and goes  
to logical ‘‘0’’ state when the counter reaches its maximum  
Y
Y
DD  
fan out of 2  
driving 74L  
or 1 driving 74LS  
TTL compatibility  
Y
Y
Parallel jam inputs  
Binary or BCD decade up/down counting  
Logic Diagram  
TL/F/5960–1  
C
1995 National Semiconductor Corporation  
TL/F/5960  
RRD-B30M105/Printed in U. S. A.  

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