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CD4029BCSJX PDF预览

CD4029BCSJX

更新时间: 2024-09-22 23:40:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 97K
描述
Synchronous Up/Down Counter

CD4029BCSJX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP16,.3Reach Compliance Code:unknown
风险等级:5.89Is Samacsys:N
计数方向:BIDIRECTIONALJESD-30 代码:R-PDSO-G16
JESD-609代码:e0负载电容(CL):50 pF
负载/预设输入:YES逻辑集成电路类型:DECADE COUNTER
最大频率@ Nom-Sup:1500000 Hz工作模式:SYNCHRONOUS
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
电源:5/15 V认证状态:Not Qualified
子类别:Counters表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

CD4029BCSJX 数据手册

 浏览型号CD4029BCSJX的Datasheet PDF文件第2页浏览型号CD4029BCSJX的Datasheet PDF文件第3页浏览型号CD4029BCSJX的Datasheet PDF文件第4页浏览型号CD4029BCSJX的Datasheet PDF文件第5页浏览型号CD4029BCSJX的Datasheet PDF文件第6页浏览型号CD4029BCSJX的Datasheet PDF文件第7页 
October 1987  
Revised January 1999  
CD4029BC  
Presettable Binary/Decade Up/Down Counter  
maximum count in the “up” mode or the minimum count in  
the “down” mode provided the carry input is at logical “0”  
state.  
General Description  
The CD4029BC is a presettable up/down counter which  
counts in either binary or decade mode depending on the  
voltage level applied at binary/decade input. When binary/  
decade is at logical “1”, the counter counts in binary, other-  
wise it counts in decade. Similarly, the counter counts up  
when the up/down input is at logical “1” and vice versa.  
All inputs are protected against static discharge by diode  
clamps to both VDD and VSS  
.
Features  
A logical “1” preset enable signal allows information at the  
“jam” inputs to preset the counter to any state asynchro-  
nously with the clock. The counter is advanced one count  
at the positive-going edge of the clock if the carry in and  
preset enable inputs are at logical “0”. Advancement is  
inhibited when either or both of these two inputs is at logi-  
cal “1”. The carry out signal is normally at logical “1” state  
and goes to logical “0” state when the counter reaches its  
Wide supply voltage range: 3V to 15V  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL compatibility: fan out of 2 driving 74L  
or 1 driving 74LS  
Parallel jam inputs  
Binary or BCD decade up/down counting  
Ordering Code:  
Order Number  
CD4029BCWM  
CD4029BCSJ  
CD4029BCN  
Package Number  
M16B  
Package Description  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide body  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
M16D  
N16E  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Assignments for DIP, SOIC and SOP  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005960.prf  
www.fairchildsemi.com  

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