5秒后页面跳转
CD4029BC PDF预览

CD4029BC

更新时间: 2024-09-22 22:54:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
8页 97K
描述
Presettable Binary/Decade Up/Down Counter

CD4029BC 数据手册

 浏览型号CD4029BC的Datasheet PDF文件第2页浏览型号CD4029BC的Datasheet PDF文件第3页浏览型号CD4029BC的Datasheet PDF文件第4页浏览型号CD4029BC的Datasheet PDF文件第5页浏览型号CD4029BC的Datasheet PDF文件第6页浏览型号CD4029BC的Datasheet PDF文件第7页 
October 1987  
Revised January 1999  
CD4029BC  
Presettable Binary/Decade Up/Down Counter  
maximum count in the “up” mode or the minimum count in  
the “down” mode provided the carry input is at logical “0”  
state.  
General Description  
The CD4029BC is a presettable up/down counter which  
counts in either binary or decade mode depending on the  
voltage level applied at binary/decade input. When binary/  
decade is at logical “1”, the counter counts in binary, other-  
wise it counts in decade. Similarly, the counter counts up  
when the up/down input is at logical “1” and vice versa.  
All inputs are protected against static discharge by diode  
clamps to both VDD and VSS  
.
Features  
A logical “1” preset enable signal allows information at the  
“jam” inputs to preset the counter to any state asynchro-  
nously with the clock. The counter is advanced one count  
at the positive-going edge of the clock if the carry in and  
preset enable inputs are at logical “0”. Advancement is  
inhibited when either or both of these two inputs is at logi-  
cal “1”. The carry out signal is normally at logical “1” state  
and goes to logical “0” state when the counter reaches its  
Wide supply voltage range: 3V to 15V  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL compatibility: fan out of 2 driving 74L  
or 1 driving 74LS  
Parallel jam inputs  
Binary or BCD decade up/down counting  
Ordering Code:  
Order Number  
CD4029BCWM  
CD4029BCSJ  
CD4029BCN  
Package Number  
M16B  
Package Description  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide body  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
M16D  
N16E  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Assignments for DIP, SOIC and SOP  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005960.prf  
www.fairchildsemi.com  

与CD4029BC相关器件

型号 品牌 获取价格 描述 数据表
CD4029BCJ NSC

获取价格

Presettable Binary/Decade Up/Down Counter
CD4029BCJ/A+ ETC

获取价格

Synchronous Up/Down Counter
CD4029BCN FAIRCHILD

获取价格

Presettable Binary/Decade Up/Down Counter
CD4029BCN NSC

获取价格

Presettable Binary/Decade Up/Down Counter
CD4029BCN/A+ ETC

获取价格

Synchronous Up/Down Counter
CD4029BCN/B+ ETC

获取价格

Synchronous Up/Down Counter
CD4029BCSJ FAIRCHILD

获取价格

Presettable Binary/Decade Up/Down Counter
CD4029BCSJX FAIRCHILD

获取价格

Synchronous Up/Down Counter
CD4029BCWM FAIRCHILD

获取价格

Presettable Binary/Decade Up/Down Counter
CD4029BCWMX ETC

获取价格

COUNTER|UP/DOWN|4-BIT BIN/DECADE|CMOS|SOP|16PIN|PLASTIC