是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Contact Manufacturer | Reach Compliance Code: | unknown |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.63 |
Is Samacsys: | N | 系列: | 4000/14000/40000 |
JESD-30 代码: | R-PDSO-G16 | JESD-609代码: | e0 |
逻辑集成电路类型: | J-K FLIP-FLOP | 位数: | 2 |
功能数量: | 2 | 端子数量: | 16 |
最高工作温度: | 125 °C | 最低工作温度: | -55 °C |
输出极性: | COMPLEMENTARY | 封装主体材料: | PLASTIC/EPOXY |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE |
峰值回流温度(摄氏度): | NOT SPECIFIED | 认证状态: | Not Qualified |
最大供电电压 (Vsup): | 18 V | 最小供电电压 (Vsup): | 3 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | MILITARY | 端子面层: | TIN LEAD |
端子形式: | GULL WING | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | NOT SPECIFIED | 触发器类型: | POSITIVE EDGE |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
CD4027B | TI |
获取价格 |
CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP | |
CD4027B_07 | TI |
获取价格 |
CMOS Dual J-K Master-Slave Flip-Flop | |
CD4027BC | NSC |
获取价格 |
Dual J-K Master/Slave Flip-Flop with Set and Reset | |
CD4027BCJ | TI |
获取价格 |
4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, | |
CD4027BCJ/A+ | ETC |
获取价格 |
J-K-Type Flip-Flop | |
CD4027BCM | FAIRCHILD |
获取价格 |
Dual J-K Master/Slave Flip-Flop with Set and Reset | |
CD4027BCM | TI |
获取价格 |
4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, | |
CD4027BCM/A+ | TI |
获取价格 |
IC,FLIP-FLOP,DUAL,J/K TYPE,CMOS,SOP,16PIN,PLASTIC | |
CD4027BCMX | ETC |
获取价格 |
FLIP-FLOP|DUAL|J/K TYPE|CMOS|SOP|16PIN|PLASTIC | |
CD4027BCN | FAIRCHILD |
获取价格 |
Dual J-K Master/Slave Flip-Flop with Set and Reset |