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CD4023M PDF预览

CD4023M

更新时间: 2024-01-09 22:46:14
品牌 Logo 应用领域
美国国家半导体 - NSC
页数 文件大小 规格书
6页 115K
描述
Triple 3-Input NAND(NOR) Gate

CD4023M 技术参数

生命周期:Transferred包装说明:,
Reach Compliance Code:unknown风险等级:5.78
Base Number Matches:1

CD4023M 数据手册

 浏览型号CD4023M的Datasheet PDF文件第2页浏览型号CD4023M的Datasheet PDF文件第3页浏览型号CD4023M的Datasheet PDF文件第4页浏览型号CD4023M的Datasheet PDF文件第5页浏览型号CD4023M的Datasheet PDF文件第6页 
February 1988  
CD4023M/CD4023C Triple 3-Input NAND Gate  
CD4025M/CD4025C Triple 3-Input NOR Gate  
General Description  
These triple gates are monolithic complementary MOS  
(CMOS) integrated circuits constructed with N- and P-chan-  
nel enhancement mode transistors. All inputs are protected  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V (typ.)  
Y
High noise immunity  
DD  
Y
5V10V parametric ratings  
against static discharge with diodes to V  
and V  
.
SS  
Y
DD  
Low power  
Connection Diagrams  
Dual-In-Line Packages  
CD4023M/CD4023C  
CD4025M/CD4025C  
TL/F/5955–1  
TL/F/5955–2  
Top View  
Top View  
Order Number CD4023 or CD4025  
C
1995 National Semiconductor Corporation  
TL/F/5955  
RRD-B30M105/Printed in U. S. A.  

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