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CD4023 PDF预览

CD4023

更新时间: 2024-11-29 22:54:19
品牌 Logo 应用领域
美国国家半导体 - NSC
页数 文件大小 规格书
6页 130K
描述
Buffered Triple 3-Input NAND,NOR Gate

CD4023 数据手册

 浏览型号CD4023的Datasheet PDF文件第2页浏览型号CD4023的Datasheet PDF文件第3页浏览型号CD4023的Datasheet PDF文件第4页浏览型号CD4023的Datasheet PDF文件第5页浏览型号CD4023的Datasheet PDF文件第6页 
February 1988  
CD4023BM/CD4023BC  
Buffered Triple 3-Input NAND Gate  
CD4025BM/CD4025BC  
Buffered Triple 3-Input NOR Gate  
General Description  
Features  
Wide supply voltage range  
High noise immunity  
Low power TTL  
Y
Y
Y
3.0V to 15V  
0.45 V (typ.)  
These triple gates are monolithic complementary MOS  
(CMOS) integrated circuits constructed with N- and P-chan-  
nel enhancement mode transistors. They have equal source  
and sink current capabilities and conform to standard B se-  
ries output drive. The devices also have buffered outputs  
which improve transfer characteristics by providing very  
high gain. All inputs are protected against static discharge  
DD  
fan out of 2 driving 74L  
or 1 driving 74LS  
compatibility  
Y
Y
Y
5V10V15V parametric ratings  
Symmetrical output characteristics  
Maximum input leakage 1 mA at 15V over full  
temperature range  
with diodes to V  
and V  
.
SS  
DD  
Connection Diagrams  
CD4023BM/CD4023BC  
Dual-In-Line Package  
CD4025BM/CD4025BC  
Dual-In-Line Package  
TL/F/5956–1  
TL/F/5956–2  
Top View  
Top View  
Order Number CD4023B or CD4025B  
C
1995 National Semiconductor Corporation  
TL/F/5956  
RRD-B30M105/Printed in U. S. A.  

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