5秒后页面跳转
CD4019BMS PDF预览

CD4019BMS

更新时间: 2024-11-02 22:56:43
品牌 Logo 应用领域
英特矽尔 - INTERSIL
页数 文件大小 规格书
9页 115K
描述
CMOS Quad AND/OR Select Gate

CD4019BMS 数据手册

 浏览型号CD4019BMS的Datasheet PDF文件第2页浏览型号CD4019BMS的Datasheet PDF文件第3页浏览型号CD4019BMS的Datasheet PDF文件第4页浏览型号CD4019BMS的Datasheet PDF文件第5页浏览型号CD4019BMS的Datasheet PDF文件第6页浏览型号CD4019BMS的Datasheet PDF文件第7页 
CD4019BMS  
CMOS Quad AND/OR Select Gate  
November 1994  
Features  
Pinout  
CD4019BMS  
TOP VIEW  
• High Voltage Type (20V Rating)  
• Medium Speed Operation tPHL = tPLH = 60ns (typ.) at  
CL = 50pF, VDD = 10V  
B4  
A3  
1
2
3
4
5
6
7
8
16 VDD  
• Standardized Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
15 A4  
B3  
14 Kb  
A2  
13 D4 = A4 Ka + B4 Kb  
12 D3 = A3 Ka + B3 Kb  
11 D2 = A2 Ka + B2 Kb  
10 D1 = A1 Ka + B1 Kb  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
B2  
A1  
B1  
• Maximum Input Current of 1µa at 18V Over Full Pack-  
age-Temperature Range;  
9
Ka  
VSS  
- 100nA at 18V and 25oC  
• Noise Margin (Over Full Package Temperature Range):  
- 1V at VDD = 5V  
Functional Diagram  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
Ka Kb  
VDD  
9
14  
16  
Applications  
15  
• And/Or Select Gating  
A4  
• Shift-Right/Shift-Left Registers  
• True/Complement Selection  
• AND/OR/Exclusive-OR Selection  
13  
D4  
D3  
D2  
D1  
1
2
3
4
5
6
7
B4  
A3  
B3  
A2  
B2  
A1  
B1  
12  
11  
10  
D4 = (A4 Ka) + (B4 Kb)  
Description  
CD4019BMS types consist of four AND/OR select gate con-  
figurations, each consisting of two 2-input AND gates driving  
a single 2-input OR gate. Selection is accomplished by con-  
trol bits Ka and Kb. In addition to selection of either channel  
A or channel B information, the control bits can be applied  
simultaneously to accomplish the logical A + B function.  
8
VSS  
The CD4019BMS is supplied in these 16-lead outline pack-  
ages:  
Braze Seal DIP  
Frit Seal DIP  
H4T  
H1E  
Ceramic Flatpack H3X  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3299  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-307  

与CD4019BMS相关器件

型号 品牌 获取价格 描述 数据表
CD4019BMT TI

获取价格

CMOS Quad AND/OR Select Gate
CD4019BMTE4 TI

获取价格

CMOS Quad AND/OR Select Gate 16-SOIC -55 to 125
CD4019BMTG4 TI

获取价格

4000/14000/40000 SERIES, QUAD 2-INPUT AND-OR GATE, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-
CD4019BMW ETC

获取价格

Quad 2-input OR Gate
CD4019BMW/883 ETC

获取价格

Quad 2-input OR Gate
CD4019BMW/883B NSC

获取价格

IC,LOGIC GATE,QUAD 2-INPUT OR,CMOS,FP,16PIN,CERAMIC
CD4019BMW/883C NSC

获取价格

IC,LOGIC GATE,QUAD 2-INPUT OR,CMOS,FP,16PIN,CERAMIC
CD4019BMW-MIL TI

获取价格

IC,LOGIC GATE,QUAD 2-INPUT OR,CMOS,FP,16PIN,CERAMIC
CD4019BNSR TI

获取价格

CMOS Quad AND/OR Select Gate
CD4019BNSRE4 TI

获取价格

4000/14000/40000 SERIES, QUAD 2-INPUT AND-OR GATE, PDSO16, GREEN, PLASTIC, SOP-16