Datasheet > CD4019BKMSR

CD4019BKMSR

更新时间： 2024-11-04 09:07:39

品牌	Logo	应用领域
瑞萨 - RENESAS		输入元件
页数	文件大小	规格书
9页	113K
描述
4000/14000/40000 SERIES, QUAD 2-INPUT AND-OR GATE, CDFP16

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数据手册

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CD4019BKMSR 数据手册

CD4019BMS

CMOS Quad AND/OR Select Gate

November 1994

Features

Pinout

CD4019BMS

TOP VIEW

• High Voltage Type (20V Rating)

• Medium Speed Operation tPHL = tPLH = 60ns (typ.) at

CL = 50pF, VDD = 10V

16 VDD

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

15 A4

14 Kb

13 D4 = A4 Ka + B4 Kb

12 D3 = A3 Ka + B3 Kb

11 D2 = A2 Ka + B2 Kb

10 D1 = A1 Ka + B1 Kb

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

• Maximum Input Current of 1µa at 18V Over Full Pack-

age-Temperature Range;

VSS

- 100nA at 18V and 25^oC

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

Functional Diagram

- 2V at VDD = 10V

- 2.5V at VDD = 15V

Ka Kb

VDD

Applications

• And/Or Select Gating

• Shift-Right/Shift-Left Registers

• True/Complement Selection

• AND/OR/Exclusive-OR Selection

D4 = (A4 Ka) + (B4 Kb)

Description

CD4019BMS types consist of four AND/OR select gate con-

ﬁgurations, each consisting of two 2-input AND gates driving

a single 2-input OR gate. Selection is accomplished by con-

trol bits Ka and Kb. In addition to selection of either channel

A or channel B information, the control bits can be applied

simultaneously to accomplish the logical A + B function.

VSS

The CD4019BMS is supplied in these 16-lead outline pack-

ages:

Braze Seal DIP

Frit Seal DIP

H4T

H1E

Ceramic Flatpack H3X

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3299

7-307

12 3 4 5 6 7...9

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