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CD4019BCSJ PDF预览

CD4019BCSJ

更新时间: 2024-11-02 22:56:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
6页 62K
描述
Quad AND-OR Select Gate

CD4019BCSJ 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.3针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.26其他特性:CONFIGURABLE AS QUAD 2:1 MUX
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
长度:10.2 mm负载电容(CL):50 pF
逻辑集成电路类型:AND-OR GATE功能数量:4
输入次数:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:5/15 V
Prop。Delay @ Nom-Sup:300 ns传播延迟(tpd):300 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.1 mm子类别:Gates
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:5.3 mm
Base Number Matches:1

CD4019BCSJ 数据手册

 浏览型号CD4019BCSJ的Datasheet PDF文件第2页浏览型号CD4019BCSJ的Datasheet PDF文件第3页浏览型号CD4019BCSJ的Datasheet PDF文件第4页浏览型号CD4019BCSJ的Datasheet PDF文件第5页浏览型号CD4019BCSJ的Datasheet PDF文件第6页 
October 1987  
Revised January 1999  
CD4019BC  
Quad AND-OR Select Gate  
General Description  
Features  
The CD4019BC is a complementary MOS quad AND-OR  
select gate. Low power and high noise margin over a wide  
voltage range is possible through implementation of N- and  
P-channel enhancement mode transistors. These comple-  
mentary MOS (CMOS) transistors provide the building  
blocks for the 4 “AND-OR select” gate configurations, each  
consisting of two 2-input AND gates driving a single 2-input  
OR gate. Selection is accomplished by control bits KA and  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL compatibility: Fan out of 2 driving 74L  
or 1 driving 74LS  
Applications  
AND-OR select gating  
KB. All inputs are protected against static discharge dam-  
age.  
Shift-right/shift-left registers  
True/complement selection  
AND/OR/EXCLUSIVE-OR selection  
Ordering Code:  
Order Number  
CD4019BCM  
CD4019BCSJ  
CD4019BCN  
Package Number  
M16A  
Package Description  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M16D  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Assignments for DIP, SOIC and SOP  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005952.prf  
www.fairchildsemi.com  

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