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CD4019BC PDF预览

CD4019BC

更新时间: 2024-11-02 22:56:43
品牌 Logo 应用领域
美国国家半导体 - NSC
页数 文件大小 规格书
4页 110K
描述
Quad AND-OR Select Gate

CD4019BC 数据手册

 浏览型号CD4019BC的Datasheet PDF文件第2页浏览型号CD4019BC的Datasheet PDF文件第3页浏览型号CD4019BC的Datasheet PDF文件第4页 
February 1988  
CD4019BM/CD4019BC Quad AND-OR Select Gate  
Features  
General Description  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V (typ.)  
The CD4019BM/CD4019BC is a complementary MOS quad  
AND-OR select gate. Low power and high noise margin  
over a wide voltage range is possible through implementa-  
tion of N- and P-channel enhancement mode transistors.  
These complementary MOS (CMOS) transistors provide the  
building blocks for the 4 ‘‘AND-OR select’’ gate configura-  
tions, each consisting of two 2-input AND gates driving a  
single 2-input OR gate. Selection is accomplished by control  
Y
High noise immunity  
DD  
Y
Low power TTL  
compatibility  
Fan out of 2 driving 74L  
or 1 driving 74LS  
Applications  
Y
AND-OR select gating  
Y
Shift-right/shift-left registers  
bits K and K . All inputs are protected against static dis-  
A
B
charge damage.  
Y
True/complement selection  
Y
AND/OR/EXCLUSIVE-OR selection  
Connection and Schematic Diagrams  
Dual-In-Line Package  
Order Number CD4019B  
TL/F/5952–1  
Top View  
TL/F/5952–2  
Schematic diagram for 1 of 4 identical stages  
C
1995 National Semiconductor Corporation  
TL/F/5952  
RRD-B30M105/Printed in U. S. A.  

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