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CD4019BC PDF预览

CD4019BC

更新时间: 2024-11-02 22:56:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
6页 62K
描述
Quad AND-OR Select Gate

CD4019BC 数据手册

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October 1987  
Revised January 1999  
CD4019BC  
Quad AND-OR Select Gate  
General Description  
Features  
The CD4019BC is a complementary MOS quad AND-OR  
select gate. Low power and high noise margin over a wide  
voltage range is possible through implementation of N- and  
P-channel enhancement mode transistors. These comple-  
mentary MOS (CMOS) transistors provide the building  
blocks for the 4 “AND-OR select” gate configurations, each  
consisting of two 2-input AND gates driving a single 2-input  
OR gate. Selection is accomplished by control bits KA and  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL compatibility: Fan out of 2 driving 74L  
or 1 driving 74LS  
Applications  
AND-OR select gating  
KB. All inputs are protected against static discharge dam-  
age.  
Shift-right/shift-left registers  
True/complement selection  
AND/OR/EXCLUSIVE-OR selection  
Ordering Code:  
Order Number  
CD4019BCM  
CD4019BCSJ  
CD4019BCN  
Package Number  
M16A  
Package Description  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M16D  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Assignments for DIP, SOIC and SOP  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005952.prf  
www.fairchildsemi.com  

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