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CD40193BFMSR PDF预览

CD40193BFMSR

更新时间： 2024-09-30 21:09:39
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
12页 151K
描述
SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDIP16, FRIT SEALED, DIP-16

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CD40193BFMSR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.72
计数方向：BIDIRECTIONALJESD-30 代码：R-GDIP-T16
JESD-609代码：e0长度：2.545 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：2000000 Hz
最大I（ol）：0.00036 A工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5/15 V
Prop。Delay @ Nom-Sup：810 ns传播延迟（tpd）：675 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class V
座面最大高度：0.56 mm子类别：Counters
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED总剂量：100k Rad(Si) V
触发器类型：POSITIVE EDGE宽度：2.045 mm
最小 fmax：1.48 MHzBase Number Matches：1

CD40193BFMSR 数据手册

 浏览型号CD40193BFMSR的Datasheet PDF文件第2页浏览型号CD40193BFMSR的Datasheet PDF文件第3页浏览型号CD40193BFMSR的Datasheet PDF文件第4页浏览型号CD40193BFMSR的Datasheet PDF文件第5页浏览型号CD40193BFMSR的Datasheet PDF文件第6页浏览型号CD40193BFMSR的Datasheet PDF文件第7页 
CD40192BMS  
CD40193BMS  
CMOS Presettable Up/Down Counters  
(Dual Clock With Reset)  
December 1992  
Features  
Description  
• CD40192BMS - BCD Type  
• CD40193BMS - Binary Type  
• High Voltage Type (20V Rating)  
CD40192BMS Presettable BCD Up/Down Counter and the  
CD40193BMS Presettable Binary Up/Down Counter each con-  
sist of 4 synchronously clocked, gated “D” type flip-flops con-  
nected as a counter. The inputs consist of 4 individual jam lines,  
a PRESET ENABLE control, individual CLOCK UP and  
CLOCK DOWN signals and a master RESET. Four buffered Q  
signal outputs as well as CARRY and BORROW outputs for  
multiple-stage counting schemes are provided.  
• Individual Clock Lines for Counting Up or Counting  
Down  
• Synchronous High-Speed Carry and Borrow Propaga-  
tion Delays for Cascading  
The counter is cleared so that all outputs are in a low state by a  
high on the RESET line. A RESET is accomplished asynchro-  
nously with the clock. Each output is individually programmable  
asynchronously with the clock to the level on the corresponding  
jam input when the PRESET ENABLE control is low.  
• Asynchronous Reset and Preset Capability  
• Medium Speed Operation  
- fCL = 8MHz (typ.) at 10V  
• 5V, 10V and 15V Parametric Ratings  
• Standardize Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
The counter counts up one count on the positive clock edge of  
the CLOCK UP signal provided the CLOCK DOWN line is high.  
The counter counts down one count on the positive clock edge  
of the CLOCK DOWN signal provided the CLOCK UP line is  
high.  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
The CARRY and BORROW signals are high when the counter  
is counting up or down. The CARRY signal goes low one-half  
clock cycle after the counter reaches its maximum count in the  
count-up mode. The BORROW signal goes low one-half clock  
cycle after the counter reaches its minimum count in the count-  
down mode. Cascading of multiple packages is easily accom-  
plished without the need for additional external circuitry by tying  
the BORROW and CARRY outputs to the CLOCK DOWN and  
CLOCK UP inputs, respectively, of the succeeding counter  
package.  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Applications  
• Up/Down Difference Counting  
• Multistage Ripple Counting  
• Synchronous Frequency Dividers  
• A/D and D/A Conversion  
The CD40192BMS and CD40193BMS are supplied in these  
16-lead outline packages:  
Braze Seal DIP  
Frit Seal DIP  
*H4W, †H4X  
H1F  
Ceramic Flatpack  
* CD40192B Only  
*H6P,  
†CD40193B Only  
†H6W  
• Programmable Binary or BCD Counting  
Functional Diagram  
Pinout  
CD40192BMS, CD40193BMS  
PRESET  
ENABLE  
TOP VIEW  
11  
15  
J1  
3
2
J2  
Q2  
Q1  
1
2
3
4
5
6
7
8
16 VDD  
Q1  
1
Q2  
15 J1  
J2  
6
10  
Q3  
14 RESET  
13 BORROW  
12 CARRY  
11 PRESET ENABLE  
10 J3  
J3  
7
9
Q4  
J4  
CLOCK DOWN  
CLOCK UP  
13  
12  
5
CLOCK UP  
4
BORROW  
CARRY  
CLOCK DOWN  
Q3  
Q4  
14  
VDD = 16  
VSS = 8  
RESET  
9
J4  
VSS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3363  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1419  
1234567...12

中文翻译

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