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CD40174BFMSR PDF预览

CD40174BFMSR

更新时间: 2024-11-15 14:48:23
品牌 Logo 应用领域
瑞萨 - RENESAS 输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 71K
描述
4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, FRIT SEALED, CERAMIC, DIP-16

CD40174BFMSR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.09
系列:4000/14000/40000JESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:9.585 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:3500000 Hz最大I(ol):0.00036 A
位数:6功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 VProp。Delay @ Nom-Sup:405 ns
传播延迟(tpd):405 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class V座面最大高度:5.33 mm
子类别:FF/Latches最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
总剂量:100k Rad(Si) V触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:3.5 MHz
Base Number Matches:1

CD40174BFMSR 数据手册

 浏览型号CD40174BFMSR的Datasheet PDF文件第2页浏览型号CD40174BFMSR的Datasheet PDF文件第3页浏览型号CD40174BFMSR的Datasheet PDF文件第4页浏览型号CD40174BFMSR的Datasheet PDF文件第5页浏览型号CD40174BFMSR的Datasheet PDF文件第6页浏览型号CD40174BFMSR的Datasheet PDF文件第7页 
CD40174BMS  
CMOS Hex ‘D’-Type Flip-Flop  
December 1992  
Features  
Pinout  
CD40174BMS  
TOP VIEW  
• High Voltage Type (20V Rating)  
• 5V, 10V and 15V Parametric Ratings  
• Standardized, Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
CLEAR  
Q1  
1
2
3
4
5
6
7
8
16 VDD  
15 Q6  
14 D6  
13 D5  
12 Q5  
11 D4  
10 Q4  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
D1  
age Temperature Range, 100nA at 18V and +25oC  
D2  
• Noise Margin (Over full Package Temperature Range):  
- 1V at VDD = 5V  
Q2  
D3  
- 2V at VDD = 10V  
Q3  
- 2.5V at VDD = 15V  
9
CLOCK  
VSS  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13A, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Applications  
Functional Diagram  
• Shift Registers  
3
2
5
D1  
Q1  
Q2  
• Buffer/Storage Registers  
• Pattern Generators  
F/F1  
F/F2  
4
D2  
Description  
CD40174BMS consists of six identical ‘D’-Type flip-flops  
having independent DATA inputs. The CLOCK and CLEAR  
inputs are common to all six units. Data is transferred to the  
Q outputs on the positive going transition of the clock pulse.  
All six flip-flops are simultaneously reset by a low level on the  
CLEAR input.  
6
7
D3  
Q3  
Q4  
Q5  
Q6  
F/F3  
F/F4  
F/F5  
F/F6  
11  
10  
12  
15  
D4  
The CD40174BMS is supplied in these 16 lead outline pack-  
ages:  
13  
D5  
Braze Seal DIP  
Frit Seal DIP  
H4T  
H1E  
14  
D5  
Ceramic Flatpack H6W  
9
CLOCK  
1
CLEAR  
VSS = 8  
VDD = 16  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3359  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1384  

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