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CD4015BC PDF预览

CD4015BC

更新时间: 2024-09-25 22:33:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器
页数 文件大小 规格书
6页 59K
描述
Dual 4-Bit Static Shift Register

CD4015BC 数据手册

 浏览型号CD4015BC的Datasheet PDF文件第2页浏览型号CD4015BC的Datasheet PDF文件第3页浏览型号CD4015BC的Datasheet PDF文件第4页浏览型号CD4015BC的Datasheet PDF文件第5页浏览型号CD4015BC的Datasheet PDF文件第6页 
October 1987  
Revised January 1999  
CD4015BC  
Dual 4-Bit Static Shift Register  
General Description  
Features  
The CD4015BC contains two identical, 4-stage, serial-  
input/parallel-output registers with independent “Data”,  
“Clock,” and “Reset” inputs. The logic level present at the  
input of each stage is transferred to the output of that stage  
at each positive-going clock transition. A logic high on the  
“Reset” input resets all four stages covered by that input.  
All inputs are protected from static discharge by a series  
Wide supply voltage range: 3.0V to 18V  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL: Fan out of 2 driving 74L  
compatibility: or 1 driving 74LS  
Medium speed operation: 8 MHz (typ.) clock rate  
Fully static design: @VDD VSS = 10V  
resistor and diode clamps to VDD and VSS  
.
Applications  
Serial-input/parallel-output data queueing  
Serial to parallel data conversion  
General purpose register  
Ordering Code:  
Order Number  
CD4015BCM  
CD4015BCN  
Package Number  
M16A  
Package Description  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
N16E  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
Pin Assignments for DIP and SOIC  
CL  
D
R
Q1  
Qn  
(Note 1)  
0
1
0
0
0
1
0
1
Qn1  
Qn1  
X
X
Q1  
0
Qn (No change)  
0
X
X = Don't Care Case  
Note 1: Level Change  
© 1999 Fairchild Semiconductor Corporation  
DS005948.prf  
www.fairchildsemi.com  

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