Datasheet > CD4013

CD4013

更新时间： 2024-09-25 11:55:03

品牌	Logo	应用领域
英特矽尔 - INTERSIL		触发器
页数	文件大小	规格书
9页	77K
描述
CMOS Dual âDâ-Type Flip-Flop

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中文翻译

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数据手册

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CD4013 数据手册

CD4013BMS

CMOS Dual ‘D’-Type Flip-Flop

December 1992

Features

Pinout

• High-Voltage Type (20V Rating)

• Set-Reset Capability

14 VDD

13 Q2

• Static Flip-Flop Operation - Retains State Indeﬁnitely

With Clock Level Either “High” Or “Low”

CLOCK 1

RESET 1

12 Q2

11 CLOCK 2

10 RESET 2

• Medium-Speed Operation - 16 MHz (typ.) Clock Toggle

Rate at 10V

SET 1

VSS

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

SET 2

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

Functional Diagram

VDD

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

SET 1

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

F/F1

F/F2

CLOCK 1

Applications

• Registers

RESET 1

SET 2

• Counters

• Control Circuits

CLOCK 2

Description

RESET 2

CD4013BMS consists of two identical, independent data

type ﬂip-ﬂops. Each ﬂip-ﬂop has independent data, set,

reset, and clock inputs and Q and Q outputs. These devices

can be used for shift register applications, and, by

connecting Q output to the data input, for counter and toggle

applications. The logic level present at the D input is

transferred to the Q output during the positive going

transition of the clock pulse. Setting or resetting is

independent of the clock and is accomplished by a high level

on the set or reset line, respectively.

VSS

The CD4013BMS is supplied in these 14 lead outline pack-

ages:

Braze Seal DIP

Frit Seal DIP

H4Q

H1B

Ceramic Flatpack H3W

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3080

7-62

12 3 4 5 6 7...9

中文翻译

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