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CD4011BCJ PDF预览

CD4011BCJ

更新时间: 2024-11-17 22:56:43
品牌 Logo 应用领域
美国国家半导体 - NSC 栅极逻辑集成电路
页数 文件大小 规格书
6页 169K
描述
Quad 2-Input NOR,NAND Buffered B Series Gate

CD4011BCJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.64
系列:4000/14000/40000JESD-30 代码:R-GDIP-T14
JESD-609代码:e0长度:19.43 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
Prop。Delay @ Nom-Sup:250 ns传播延迟(tpd):250 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

CD4011BCJ 数据手册

 浏览型号CD4011BCJ的Datasheet PDF文件第2页浏览型号CD4011BCJ的Datasheet PDF文件第3页浏览型号CD4011BCJ的Datasheet PDF文件第4页浏览型号CD4011BCJ的Datasheet PDF文件第5页浏览型号CD4011BCJ的Datasheet PDF文件第6页 
March 1988  
CD4001BM/CD4001BC Quad 2-Input  
NOR Buffered B Series Gate  
CD4011BM/CD4011BC Quad 2-Input  
NAND Buffered B Series Gate  
General Description  
Features  
Y
Low power TTL  
compatibility  
Fan out of 2 driving 74L  
or 1 driving 74LS  
These quad gates are monolithic complementary MOS  
(CMOS) integrated circuits constructed with N- and P-chan-  
nel enhancement mode transistors. They have equal source  
and sink current capabilities and conform to standard B se-  
ries output drive. The devices also have buffered outputs  
which improve transfer characteristics by providing very  
high gain.  
Y
5V10V15V parametric ratings  
Y
Symmetrical output characteristics  
Maximum input leakage 1 mA at 15V over full tempera-  
ture range  
Y
All inputs are protected against static discharge with diodes  
.
SS  
to V  
and V  
DD  
Schematic Diagrams  
CD4001BC/BM  
(/4 of device shown  
e
a
B
J
A
e
e
Logical ‘‘1’’  
Logical ‘‘0’’  
High  
Low  
TL/F/5939–2  
*All inputs protected by standard  
CMOS protection circuit.  
TL/F/5939–1  
CD4011BC/BM  
(/4 of device shown  
e
J
A
B
#
e
e
Logical ‘‘1’’  
Logical ‘‘0’’  
High  
Low  
TL/F/5939–6  
*All inputs protected by standard  
CMOS protection circuit.  
TL/F/5939–5  
C
1995 National Semiconductor Corporation  
TL/F/5939  
RRD-B30M105/Printed in U. S. A.  

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