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CBTV4020EE/G PDF预览

CBTV4020EE/G

更新时间: 2024-11-16 12:59:55
品牌 Logo 应用领域
恩智浦 - NXP 动态存储器双倍数据速率
页数 文件大小 规格书
16页 98K
描述
IC DDR DRAM, PDSO72, 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, TFBGA-72, Dynamic RAM

CBTV4020EE/G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, TFBGA-72
针数:72Reach Compliance Code:unknown
风险等级:5.81JESD-30 代码:S-PDSO-G72
内存集成电路类型:DDR DRAM端子数量:72
封装主体材料:PLASTIC/EPOXY封装形状:SQUARE
封装形式:SMALL OUTLINE认证状态:Not Qualified
表面贴装:YES端子形式:GULL WING
端子位置:DUALBase Number Matches:1

CBTV4020EE/G 数据手册

 浏览型号CBTV4020EE/G的Datasheet PDF文件第2页浏览型号CBTV4020EE/G的Datasheet PDF文件第3页浏览型号CBTV4020EE/G的Datasheet PDF文件第4页浏览型号CBTV4020EE/G的Datasheet PDF文件第5页浏览型号CBTV4020EE/G的Datasheet PDF文件第6页浏览型号CBTV4020EE/G的Datasheet PDF文件第7页 
CBTV4020  
20-bit DDR SDRAM 2 : 1 MUX  
Rev. 03 — 4 April 2008  
Product data sheet  
1. General description  
This 20-bit bus switch is designed for 2.3 V to 2.7 V VDD operation and SSTL_2 select  
input levels.  
Each host port pin is multiplexed to one of two DIMM port pins. When the SEL pin is HIGH  
the A DIMM port is turned on and the B DIMM port is off. The ON-state connects the host  
port to the DIMM port through a 20 nominal series resistance. When the port is off a  
high-impedance state exists between the Host and disabled DIMM. The DIMM port is  
terminated with a 100 resistor to ground. When the SEL pin is LOW the B DIMM port is  
turned on and the A DIMM port is off.  
The part incorporates a very low crosstalk design. It has a very low skew between outputs  
(< 50 ps) and low skew (< 50 ps) for rising and falling edges. The part has optimal  
performance in DDR data bus applications.  
Each switch has been optimized for connection to 1-bank or 2-bank DIMMs.  
The low internal RC time constant of the switch (20 Ω × 7 pF) allows data transfer to be  
made with minimal propagation delay.  
The CBTV4020 is characterized for operation from 0 °C to +85 °C.  
2. Features  
I SEL signal is SSTL_2 compatible  
I Optimized for use in Double Data Rate (DDR) SDRAM applications  
I Designed to be used with 400 Mbit/s 200 MHz DDR data bus  
I Switch ON resistance is designed to eliminate the need for series resistor to DDR  
SDRAM  
I RON ~ 20 Ω  
I Internal 100 pull-down resistors on DIMM side when path is disabled  
I Low differential skew  
I Matched rise/fall slew rate  
I Low crosstalk  
I One DIMM select control line  
I Latch-up protection exceeds 500 mA per JESD78  
I ESD protection exceeds 1500 V HBM per JESD22-A114, 200 V MM per  
JESD22-A115 and 1000 V CDM per JESD22-C101  

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