Datasheet > CBTV24DD12ETY

CBTV24DD12ETY

更新时间： 2024-09-20 14:49:59

品牌	Logo	应用领域
恩智浦 - NXP		PC 双倍数据速率电视
页数	文件大小	规格书
19页	660K
描述
CBTV24DD12 - 12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications BGA 48-Pin

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技术参数
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CBTV24DD12ETY 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	3 X 8 MM,1 MM HEIGHT, 0.65 MM PITCH, GREEN, PLASTIC, SOT1365-1, TFBGA-48
针数：	48	Reach Compliance Code：	compliant
风险等级：	1.63	Samacsys Confidence：	4
Samacsys Status：	Released	Samacsys PartID：	1423010
Samacsys Pin Count：	48	Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	BGA	Samacsys Footprint Name：	TFBGA48 (SOT1365-1)
Samacsys Released Date：	2019-07-31 12:48:34	Is Samacsys：	N
Base Number Matches：	1

CBTV24DD12ETY 数据手册

CBTV24DD12

12-bit bus switch/multiplexer for DDR4-DDR3-DDR2

applications

Rev. 3.2 — 19 April 2016

Product data sheet

1. General description

CBTV24DD12 is designed for 1.8 V/2.5 V/3.3 V supply voltage operation and it supports

Pseudo Open Drain (POD), SSTL_12, SSTL_15 or SSTL_18 signaling and CMOS select

input levels. This device is designed for operation in DDR4, DDR3 or DDR2 memory bus

systems, with speeds up to 3200 MT/s.

The CBTV24DD12 has a 1 : 2 switch or 2 : 1 multiplex topology and offers a 12-bit wide

bus. Each 12-bit wide A-port can be switched to one of two ports B and C, for all bits

simultaneously. Each port is non-directional due to the use of FET switches, allowing a

multitude of applications requiring high-bandwidth switching or multiplexing.

The selection of the port is by a simple CMOS input (SELect). Another CMOS input

(ENable) is available to allow all ports to be disconnected. The SEL0, SEL1 and EN input

signals are designed to operate transparently as CMOS input level signals up to 3.3 V.

CBTV24DD12 uses NXP’s proprietary high-speed switch architecture providing high

bandwidth, very little insertion loss, return loss, and very low propagation delay, allowing

use in many applications requiring switching or multiplexing of high-speed signals. It is

available in a 3.0 mm  8.0 mm TFBGA48 package with 0.65 mm ball pitch, for optimal

size versus board layout density considerations. It is characterized for operation from

10 C to +85 C.

2. Features and benefits

2.1 Topology

 12-bit bus width

 1 : 2 switch/MUX topology

 Bidirectional operation

 Simple CMOS select pins (SEL0, SEL1)

 Simple CMOS enable pin (EN)

2.2 Performance

 3200 MT/s throughput

 7.4 GHz bandwidth (for both single-ended and differential signals)

 Low ON insertion loss

 Low return loss

 Low crosstalk

 High OFF isolation

12 3 4 5 6 7...19

中文翻译

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与CBTV24DD12ETY相关器件

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