Datasheet > CBTU4411EE/G,551

CBTU4411EE/G,551

更新时间： 2024-09-29 15:42:59

品牌	Logo	应用领域
恩智浦 - NXP		动态存储器双倍数据速率
页数	文件大小	规格书
21页	130K
描述
CBTU4411 - 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance BGA 72-Pin

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CBTU4411EE/G,551 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	7 X 7 MM, 1.05 MM HEIGHT, PLASTIC, SOT856-1, LFBGA-72
针数：	72	Reach Compliance Code：	unknown
风险等级：	5.84	Base Number Matches：	1

CBTU4411EE/G,551 数据手册

CBTU4411

11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance

Rev. 4 — 18 June 2012

Product data sheet

1. General description

This 11-bit bus switch is designed for 1.7 V to 1.9 V V_DDoperation and SSTL_18 select

input levels.

Each Host port pin (HPn) is multiplexed to one of four DIMM port pins (xDPn). The

selection of the DIMM port to be connected to the Host port is controlled by a decoder

driven by three hardware select pins S0, S1 and EN. Driving pin EN HIGH disconnects all

DIMM ports from their respective host ports. When EN is driven LOW, pins S0 and S1

select one of four DIMM ports to be connected to their respective host port. When

disconnected, any DIMM port is terminated to the externally supplied voltage V_biasby

means of an on-chip pull-down resistor of typically 400 Ω. The ON-state connects the

Host port to the DIMM port through a 12 Ω nominal series resistance. The design is

intended to have only one DIMM port active at any time.

The CBTU4411 can also be configured to support a differential strobe signal on

channel 10 (TRUE) and channel 9 (complementary Strobe). When its LVCMOS

configuration input strobe enable (STREN) is HIGH, channel 10 is pulled up to ³⁄₄of V_DD

internally by a resistive divider when the DIMM port is idle. When the CBTU4411 is

disabled (EN = HIGH in Strobe mode), the pull-down on channel 10 is disabled for current

savings, pulling channel 10 to V_DD. When strobe enable (STREN) is LOW, channel 10

behaves the same as all other channels.

The select inputs (S0, S1) are pseudo-differential type SSTL_18. A reference voltage

should be provided to input pin VREF at nominally 0.5V_DD. This topology provides

accurate control of switching times by reducing dependency on select signal slew rates.

S0 and S1 are provided with selectable input termination to 0.5V_DD(active when LVCMOS

input TERM is HIGH). When the CBTU4411 is disabled (EN = HIGH), both S0 and S1

inputs are pulled LOW.

The part incorporates a very low crosstalk design. It has a very low skew between outputs

(< 30 ps) and low skew (< 30 ps) for rising and falling edges. The part has optimal

performance in DDR2 data bus applications.

Each switch has been optimized for connection to 1- or 2-rank DIMMs.

The low internal RC time constant of the switch allows data transfer to be made with

minimal propagation delay.

The CBTU4411 is characterized for operation from 0 °C to +85 °C.

12 3 4 5 6 7...21

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与CBTU4411EE/G,551相关器件

型号	品牌	获取价格	描述	数据表
CBTV24DD12AET	NXP	获取价格	12-Bit Bus Switch/Multiplexer for DDR4-DDR3-DDR2 Applications
CBTV24DD12ET	NXP	获取价格	12-Bit Bus Switch/Multiplexer for DDR4-DDR3-DDR2 Applications
CBTV24DD12ETY	NXP	获取价格	CBTV24DD12 - 12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications BGA 48-Pin
CBTV4010	NXP	获取价格	10-bit DDR SDRAM mux/bus switch
CBTV4010EE	NXP	获取价格	IC 4000/14000/40000 SERIES, 10-BIT DRIVER, TRUE OUTPUT, PBGA64, PLASTIC, TFBGA-64, Bus Dri
CBTV4010EE,551	NXP	获取价格	CBTV4010EE
CBTV4020	NXP	获取价格	20-bit DDR SDRAM 2 : 1 MUX
CBTV4020EE	NXP	获取价格	20-bit DDR SDRAM 2 : 1 MUX
CBTV4020EE/G	NXP	获取价格	IC DDR DRAM, PDSO72, 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, TFBGA-72, Dynamic RAM
CBTV4020EG	NXP	获取价格	20-bit DDR SDRAM 2 : 1 MUX

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