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CBTU4411EE,551 PDF预览

CBTU4411EE,551

更新时间： 2024-11-16 15:29:15
品牌 Logo 应用领域
恩智浦 - NXP 动态存储器双倍数据速率逻辑集成电路
页数 文件大小 规格书
21页 143K
描述
CBTU4411 - 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance BGA 72-Pin

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CBTU4411EE,551 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：LFBGA, BGA72,11X11,20
针数：72Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.84
系列：CBT/FST/QS/5C/BJESD-30 代码：S-PBGA-B72
JESD-609代码：e1长度：7 mm
逻辑集成电路类型：BUS TRANSCEIVER湿度敏感等级：3
位数：11功能数量：1
端口数量：2端子数量：72
最高工作温度：85 °C最低工作温度：
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA72,11X11,20封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：1.8 V传播延迟（tpd）：0.1 ns
认证状态：Not Qualified座面最大高度：1.5 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：7 mmBase Number Matches：1

CBTU4411EE,551 数据手册

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CBTU4411  
11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance  
Rev. 4 — 18 June 2012  
Product data sheet  
1. General description  
This 11-bit bus switch is designed for 1.7 V to 1.9 V VDD operation and SSTL_18 select  
input levels.  
Each Host port pin (HPn) is multiplexed to one of four DIMM port pins (xDPn). The  
selection of the DIMM port to be connected to the Host port is controlled by a decoder  
driven by three hardware select pins S0, S1 and EN. Driving pin EN HIGH disconnects all  
DIMM ports from their respective host ports. When EN is driven LOW, pins S0 and S1  
select one of four DIMM ports to be connected to their respective host port. When  
disconnected, any DIMM port is terminated to the externally supplied voltage Vbias by  
means of an on-chip pull-down resistor of typically 400 Ω. The ON-state connects the  
Host port to the DIMM port through a 12 Ω nominal series resistance. The design is  
intended to have only one DIMM port active at any time.  
The CBTU4411 can also be configured to support a differential strobe signal on  
channel 10 (TRUE) and channel 9 (complementary Strobe). When its LVCMOS  
configuration input strobe enable (STREN) is HIGH, channel 10 is pulled up to 3⁄4 of VDD  
internally by a resistive divider when the DIMM port is idle. When the CBTU4411 is  
disabled (EN = HIGH in Strobe mode), the pull-down on channel 10 is disabled for current  
savings, pulling channel 10 to VDD. When strobe enable (STREN) is LOW, channel 10  
behaves the same as all other channels.  
The select inputs (S0, S1) are pseudo-differential type SSTL_18. A reference voltage  
should be provided to input pin VREF at nominally 0.5VDD. This topology provides  
accurate control of switching times by reducing dependency on select signal slew rates.  
S0 and S1 are provided with selectable input termination to 0.5VDD (active when LVCMOS  
input TERM is HIGH). When the CBTU4411 is disabled (EN = HIGH), both S0 and S1  
inputs are pulled LOW.  
The part incorporates a very low crosstalk design. It has a very low skew between outputs  
(< 30 ps) and low skew (< 30 ps) for rising and falling edges. The part has optimal  
performance in DDR2 data bus applications.  
Each switch has been optimized for connection to 1- or 2-rank DIMMs.  
The low internal RC time constant of the switch allows data transfer to be made with  
minimal propagation delay.  
The CBTU4411 is characterized for operation from 0 °C to +85 °C.  
 
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CBTU4411EE,551 替代型号

型号 品牌 替代类型 描述 数据表
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