Datasheet > CBTU4411_09

CBTU4411_09

更新时间： 2024-09-29 06:46:27

品牌	Logo	应用领域
恩智浦 - NXP		开关动态存储器双倍数据速率
页数	文件大小	规格书
20页	108K
描述
11-bit DDR2 SDRAM MUX/bus switch with 12 W ON resistance

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CBTU4411_09 数据手册

CBTU4411

11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance

Rev. 03 — 12 October 2009

Product data sheet

1. General description

This 11-bit bus switch is designed for 1.7 V to 1.9 V V_DDoperation and SSTL_18 select

input levels.

Each Host port pin (HPn) is multiplexed to one of four DIMM port pins (xDPn). The

selection of the DIMM port to be connected to the Host port is controlled by a decoder

driven by three hardware select pins S0, S1 and EN. Driving pin EN HIGH disconnects all

DIMM ports from their respective host ports. When EN is driven LOW, pins S0 and S1

select one of four DIMM ports to be connected to their respective host port. When

disconnected, any DIMM port is terminated to the externally supplied voltage V_biasby

means of an on-chip pull-down resistor of typically 400 Ω. The ON-state connects the

Host port to the DIMM port through a 12 Ω nominal series resistance. The design is

intended to have only one DIMM port active at any time.

The CBTU4411 can also be conﬁgured to support a differential strobe signal on

channel 10 (TRUE) and channel 9 (complementary Strobe). When its LVCMOS

conﬁguration input strobe enable (STREN) is HIGH, channel 10 is pulled up to ³⁄₄of V_DD

internally by a resistive divider when the DIMM port is idle. When the CBTU4411 is

disabled (EN = HIGH in Strobe mode), the pull-down on channel 10 is disabled for current

savings, pulling channel 10 to V_DD. When strobe enable (STREN) is LOW, channel 10

behaves the same as all other channels.

The select inputs (S0, S1) are pseudo-differential type SSTL_18. A reference voltage

should be provided to input pin VREF at nominally 0.5V_DD. This topology provides

accurate control of switching times by reducing dependency on select signal slew rates.

S0 and S1 are provided with selectable input termination to 0.5V_DD(active when LVCMOS

input TERM is HIGH). When the CBTU4411 is disabled (EN = HIGH), both S0 and S1

inputs are pulled LOW.

The part incorporates a very low crosstalk design. It has a very low skew between outputs

(< 30 ps) and low skew (< 30 ps) for rising and falling edges. The part has optimal

performance in DDR2 data bus applications.

Each switch has been optimized for connection to 1- or 2-rank DIMMs.

The low internal RC time constant of the switch allows data transfer to be made with

minimal propagation delay.

The CBTU4411 is characterized for operation from 0 °C to +85 °C.

12 3 4 5 6 7...20

中文翻译

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与CBTU4411_09相关器件

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CBTU4411EE	NXP	获取价格	11-bit DDR2 SDRAM MUX/bus switch with 12 ohm ON resistance
CBTU4411EE,518	NXP	获取价格	CBTU4411 - 11-bit DDR2 SDRAM MUX/bus switch w
CBTU4411EE,551	NXP	获取价格	CBTU4411 - 11-bit DDR2 SDRAM MUX/bus switch w
CBTU4411EE,557	NXP	获取价格	CBTU4411 - 11-bit DDR2 SDRAM MUX/bus switch w
CBTU4411EE/G,118	NXP	获取价格	CBTU4411 - 11-bit DDR2 SDRAM MUX/bus switch w
CBTU4411EE/G,518	NXP	获取价格	CBTU4411 - 11-bit DDR2 SDRAM MUX/bus switch w
CBTU4411EE/G,551	NXP	获取价格	CBTU4411 - 11-bit DDR2 SDRAM MUX/bus switch w
CBTV24DD12AET	NXP	获取价格	12-Bit Bus Switch/Multiplexer for DDR4-DDR3-DDR2 Applications
CBTV24DD12ET	NXP	获取价格	12-Bit Bus Switch/Multiplexer for DDR4-DDR3-DDR2 Applications
CBTV24DD12ETY	NXP	获取价格	CBTV24DD12 - 12-bit bus switch/multiplexer for DDR4-DDR3-DDR2 applications BGA 48-Pin

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