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CAV24C512HU5EGT3 PDF预览

CAV24C512HU5EGT3

更新时间: 2024-12-01 01:05:15
品牌 Logo 应用领域
安森美 - ONSEMI 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
13页 120K
描述
512 kb I2C CMOS Serial EEPROM

CAV24C512HU5EGT3 技术参数

是否无铅: 不含铅生命周期:Not Recommended
包装说明:UDFN-8Reach Compliance Code:compliant
Factory Lead Time:8 weeks风险等级:5.72
最大时钟频率 (fCLK):1 MHzJESD-30 代码:R-PDSO-N8
JESD-609代码:e4长度:3 mm
内存密度:524288 bit内存集成电路类型:EEPROM
内存宽度:8湿度敏感等级:1
功能数量:1端子数量:8
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-40 °C组织:64KX8
封装主体材料:PLASTIC/EPOXY封装代码:HVSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
并行/串行:SERIAL峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:0.55 mm串行总线类型:I2C
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:2 mm
最长写入周期时间 (tWC):5 msBase Number Matches:1

CAV24C512HU5EGT3 数据手册

 浏览型号CAV24C512HU5EGT3的Datasheet PDF文件第2页浏览型号CAV24C512HU5EGT3的Datasheet PDF文件第3页浏览型号CAV24C512HU5EGT3的Datasheet PDF文件第4页浏览型号CAV24C512HU5EGT3的Datasheet PDF文件第5页浏览型号CAV24C512HU5EGT3的Datasheet PDF文件第6页浏览型号CAV24C512HU5EGT3的Datasheet PDF文件第7页 
CAV24C512  
512 kb I2C CMOS Serial  
EEPROM  
Description  
The CAV24C512 is a 512 kb Serial CMOS EEPROM, internally  
organized as 65,536 words of 8 bits each.  
www.onsemi.com  
It features a 128−byte page write buffer and supports the Standard  
2
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I C protocol.  
Write operations can be inhibited by taking the WP pin High (this  
protects the entire memory).  
External address pins make it possible to address up to eight  
CAV24C512 devices on the same bus.  
On−Chip ECC (Error Correction Code) makes the device suitable  
for high reliability applications.  
SOIC−8  
W SUFFIX  
CASE 751BD  
UDFN−8  
HU5 SUFFIX  
CASE 517BU  
Features  
Automotive Temperature Grade 1 (−40°C to +125°C)  
2
TSSOP−8  
Y SUFFIX  
CASE 948AL  
WLCSP−8  
C8A SUFFIX  
CASE 567JL  
Supports Standard, Fast and Fast−Plus I C Protocol  
2.5 V to 5.5 V Supply Voltage Range  
128−Byte Page Write Buffer  
Hardware Write Protection for Entire Memory  
PIN CONFIGURATIONS  
2
Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs  
Pin A1  
Reference  
A
A
A
V
CC  
0
1
2
(SCL and SDA)  
1
WP  
Low Power CMOS Technology  
1,000,000 Program/Erase Cycles  
100 Year Data Retention  
8−lead SOIC, TSSOP, UDFN and 8−ball WLCSP Packages  
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
SCL  
SDA  
SDA  
VCC  
WP  
V
SS  
SCL  
A
2
SOIC (W, X), TSSOP (Y),  
UDFN (HU5)  
A
1
(Top View)  
A
0
VSS  
V
CC  
For the location of  
Pin 1, please consult  
the corresponding  
package drawing.  
WLCSP (C8A)  
(Top View)  
SCL  
CAV24C512  
SDA  
PIN FUNCTION  
A , A , A  
2
1
0
Pin Name  
Function  
Device Address  
WP  
A , A , A  
0
1
2
SDA  
Serial Data  
Serial Clock  
Write Protect  
Power Supply  
Ground  
V
SS  
SCL  
WP  
Figure 1. Functional Symbol  
V
CC  
V
SS  
This document contains information on some products that are still under development.  
ON Semiconductor reserves the right to change or discontinue these products without  
notice.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 13 of this data sheet.  
© Semiconductor Components Industries, LLC, 2016  
1
Publication Order Number:  
February, 2016 − Rev. 2  
CAV24C512/D  

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