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CAT93C66MA1.8 PDF预览

CAT93C66MA1.8

更新时间： 2024-11-19 20:29:47
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
10页 67K
描述
EEPROM

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中文翻译

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CAT93C66MA1.8 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknown风险等级：5.84
Base Number Matches：1

CAT93C66MA1.8 数据手册

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"GREEN" PACKAGES  
CAT93C46/56/57/66/86  
-Lead free  
1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM  
FEATURES  
ꢀ High speed operation:  
ꢀ Power-up inadvertant write protection  
ꢀ 1,000,000 Program/erase cycles  
ꢀ 100 year data retention  
– 93C56/57/66: 1MHz  
– 93C46/86: 3MHz  
ꢀ Low power CMOS technology  
ꢀ Commercial, industrial and automotive  
ꢀ 1.8 to 6.0 volt operation  
temperature ranges  
ꢀ Selectable x8 or x16 memory organization  
ꢀ Self-timed write cycle with auto-clear  
ꢀ Hardware and software write protection  
ꢀ Sequential read (except CAT93C46)  
ꢀꢀꢀProgram enable (PE) pin (CAT93C86 only)  
ꢀꢀꢀAvailable in new lead-free packages  
DESCRIPTION  
CMOS EEPROM floating gate technology. The devices  
aredesignedtoendure1,000,000program/erasecycles  
and have a data retention of 100 years. The devices are  
available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP  
packages.  
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit  
Serial EEPROM memory devices which are configured  
as either registers of 16 bits (ORG pin at VCC) or 8 bits  
(ORGpinatGND). Eachregistercanbewritten(orread)  
serially by using the DI (or DO) pin. The CAT93C46/56/  
57/66/86 are manufactured using Catalyst’s advanced  
PIN CONFIGURATION  
TSSOP Package (U,Y)  
SOIC Package (J,W) SOIC Package (S,V)  
DIP Package (P, L)  
SOIC Package (K,X)  
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
CC  
NC (PE*)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
ORG  
GND  
DO  
CS  
SK  
DI  
V
CS  
SK  
DI  
V
CC  
NC (PE*)  
CC  
CC  
NC (PE*)  
ORG  
V
NC (PE*)  
ORG  
NC (PE*)  
ORG  
CC  
ORG  
CS  
DO  
DO  
GND  
SK  
DI  
DO  
GND  
DO  
GND  
GND  
*Only For 93C86  
93C46/56/57/66/86  
F01  
PIN FUNCTIONS  
BLOCK DIAGRAM  
Pin Name  
CS  
Function  
V
GND  
CC  
Chip Select  
SK  
Clock Input  
ADDRESS  
DECODER  
DI  
Serial Data Input  
Serial Data Output  
MEMORY ARRAY  
ORGANIZATION  
ORG  
DO  
VCC  
GND  
ORG  
NC  
+1.8 to 6.0V Power Supply  
Ground  
DATA  
REGISTER  
OUTPUT  
BUFFER  
Memory Organization  
No Connection  
DI  
MODE DECODE  
LOGIC  
CS  
PE*  
PE*  
Program Enable  
Note: When the ORG pin is connected to VCC, the X16 organiza  
tion is selected. When it is connected to ground, the X8 pin  
is selected. If the ORG pin is left unconnected, then an  
internal pullup device will select the X16 organization.  
CLOCK  
GENERATOR  
DO  
SK  
93C46/56/57/66/86 F02  
© 2002 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice.  
Doc. No. 1023, Rev. D  
1234567...10

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