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CAT93C56UA-1.8TE13REVE PDF预览

CAT93C56UA-1.8TE13REVE

更新时间: 2024-11-25 13:06:39
品牌 Logo 应用领域
CATALYST 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
9页 65K
描述
128KX16 MICROWIRE BUS SERIAL EEPROM, PDSO8, TSSOP-8

CAT93C56UA-1.8TE13REVE 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:TSSOP-8
针数:8Reach Compliance Code:unknown
风险等级:5.64Is Samacsys:N
备用内存宽度:8最大时钟频率 (fCLK):0.25 MHz
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.4 mm内存密度:2097152 bit
内存集成电路类型:EEPROM内存宽度:16
功能数量:1端子数量:8
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:105 °C
最低工作温度:-40 °C组织:128KX16
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:SERIAL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.2 mm
串行总线类型:MICROWIRE最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3 mmBase Number Matches:1

CAT93C56UA-1.8TE13REVE 数据手册

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CAT93C46/56/57/66/86  
1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM  
FEATURES  
High Speed Operation:  
Power-Up Inadvertant Write Protection  
1,000,000 Program/Erase Cycles  
100 Year Data Retention  
– 93C46/56/57/66: 1MHz  
– 93C86: 3MHz  
Low Power CMOS Technology  
Commercial, Industrial and Automotive  
1.8 to 6.0 Volt Operation  
Temperature Ranges  
Selectable x8 or x16 Memory Organization  
Self-Timed Write Cycle with Auto-Clear  
Hardware and Software Write Protection  
Sequential Read (except 93C46)  
Program Enable (PE) Pin (93C86 only)  
DESCRIPTION  
CMOS E2PROM floating gate technology. The devices  
aredesignedtoendure1,000,000program/erasecycles  
and have a data retention of 100 years. The devices are  
available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP  
packages.  
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit  
Serial E2PROM memory devices which are configured  
as either registers of 16 bits (ORG pin at VCC) or 8 bits  
(ORGpinatGND). Eachregistercanbewritten(orread)  
serially by using the DI (or DO) pin. The CAT93C46/56/  
57/66/86 are manufactured using Catalyst’s advanced  
PIN CONFIGURATION  
TSSOP Package (U)  
SOIC Package (J)  
SOIC Package (S)  
DIP Package (P)  
SOIC Package (K)  
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
CC  
NC (PE*)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
ORG  
GND  
DO  
CS  
SK  
DI  
V
CS  
SK  
DI  
V
CC  
NC (PE*)  
CC  
CC  
NC (PE*)  
V
NC (PE*)  
ORG  
NC (PE*)  
ORG  
CC  
ORG  
ORG  
CS  
DO  
DO  
GND  
SK  
DI  
DO  
GND  
DO  
GND  
GND  
*Only For 93C86  
93C46/56/57/66/86  
F01  
PIN FUNCTIONS  
BLOCK DIAGRAM  
Pin Name  
CS  
Function  
V
GND  
CC  
Chip Select  
SK  
Clock Input  
ADDRESS  
DECODER  
DI  
Serial Data Input  
Serial Data Output  
MEMORY ARRAY  
ORGANIZATION  
ORG  
DO  
VCC  
GND  
ORG  
NC  
+1.8 to 6.0V Power Supply  
Ground  
DATA  
REGISTER  
OUTPUT  
BUFFER  
Memory Organization  
No Connection  
DI  
MODE DECODE  
LOGIC  
CS  
PE*  
PE*  
Program Enable  
Note: When the ORG pin is connected to VCC, the X16 organiza  
tion is selected. When it is connected to ground, the X8 pin  
is selected. If the ORG pin is left unconnected, then an  
internal pullup device will select the X16 organization.  
CLOCK  
GENERATOR  
DO  
SK  
93C46/56/57/66/86 F02  
© 1998 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 25056-00 2/98 M-1  
1

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