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CAT93C56LI-REVE PDF预览

CAT93C56LI-REVE

更新时间: 2024-11-26 18:35:03
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
18页 246K
描述
EEPROM, 128X16, Serial, CMOS, PDIP8, 0.300 INCH, GREEN, PLASTIC, MS-001, DIP-8

CAT93C56LI-REVE 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.24备用内存宽度:8
最大时钟频率 (fCLK):0.5 MHzJESD-30 代码:R-PDIP-T8
JESD-609代码:e3长度:9.59 mm
内存密度:2048 bit内存集成电路类型:EEPROM
内存宽度:16功能数量:1
端子数量:8字数:128 words
字数代码:128工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128X16封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:5.33 mm串行总线类型:MICROWIRE
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.62 mm
Base Number Matches:1

CAT93C56LI-REVE 数据手册

 浏览型号CAT93C56LI-REVE的Datasheet PDF文件第2页浏览型号CAT93C56LI-REVE的Datasheet PDF文件第3页浏览型号CAT93C56LI-REVE的Datasheet PDF文件第4页浏览型号CAT93C56LI-REVE的Datasheet PDF文件第5页浏览型号CAT93C56LI-REVE的Datasheet PDF文件第6页浏览型号CAT93C56LI-REVE的Datasheet PDF文件第7页 
CAT93C56, CAT93C57  
2-Kb Microwire Serial CMOS EEPROM  
FEATURES  
DESCRIPTION  
The CAT93C56/57 is a 2-Kb CMOS Serial EEPROM  
device which is organized as either 128 registers of 16  
bits (ORG pin at VCC) or 256 registers of 8 bits (ORG pin  
at GND). Each register can be written (or read) serially  
by using the DI (or DO) pin. The CAT93C56/57 features  
sequential read and self-timed internal write with auto-  
clear. On-chip Power-On Reset circuitry protects the  
internal logic against powering up in the wrong state.  
„ High speed operation: 2MHz  
„ 1.8V to 5.5V supply voltage range  
„ Selectable x8 or x16 memory organization  
„ Sequential read  
„ Software write protection  
„ Power-up inadvertant write protection  
„ Low power CMOS technology  
„ 1,000,000 Program/erase cycles  
„ 100 year data retention  
„ Industrial and Extended temperature ranges  
For Ordering Information details, see page 16.  
„ RoHS-compliant 8-pin PDIP, SOIC, TSSOP and  
8-pad TDFN packages  
FUNCTIONAL SYMBOL  
PIN CONFIGURATION  
PDIP (L)  
SOIC (V, X)  
TSSOP (Y)  
VCC  
TDFN (VP2, ZD4*)  
SOIC (W*)  
ORG  
CS  
SK  
DI  
1
2
3
4
8
7
6
5
VCC  
NC  
VCC  
CS  
SK  
1
2
3
4
8
7
6
5
ORG  
GND  
DO  
CS  
SK  
DI  
DO  
CAT93C56  
CAT93C57  
NC  
ORG  
GND  
DO  
DI  
* TDFN 3x3mm (ZD4) and SOIC (W) rotated pin-out packages are  
available for CAT93C57 and CAT93C56, Rev. E only (not  
recommended for new designs of CAT93C56)  
GND  
PIN FUNCTION  
Pin Name  
CS  
Function  
Chip Select  
SK  
Clock Input  
DI  
Serial Data Input  
Serial Data Output  
Power Supply  
Ground  
DO  
VCC  
GND  
ORG  
NC  
Note: When the ORG pin is connected to VCC, the x16 organization  
is selected. When it is connected to ground, the x8 pin is selected. If  
the ORG pin is left unconnected, then am internal pullup device will  
select the x16 organization  
Memory Organization  
No Connection  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
1
Doc. No. MD-1088 Rev. Q  

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