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CAT5401Y-10-TE13

更新时间： 2024-12-01 14:37:43
品牌 Logo 应用领域
CATALYST 光电二极管转换器电阻器
页数 文件大小 规格书
16页 105K
描述
Digital Potentiometer, 4 Func, 10000ohm, 3-wire Serial Control Interface, 64 Positions, CMOS, PDSO24, TSSOP-24

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CAT5401Y-10-TE13 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：TSSOP包装说明：LSSOP, TSSOP24,.25
针数：24Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.11其他特性：NONVOLATILE MEMORY
控制接口：3-WIRE SERIAL转换器类型：DIGITAL POTENTIOMETER
JESD-30 代码：R-PDSO-G24JESD-609代码：e3
长度：7.8 mm湿度敏感等级：1
功能数量：4位置数：64
端子数量：24最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：LSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified电阻定律：LINEAR
最大电阻容差：20%最大电阻器端电压：3 V
最小电阻器端电压：座面最大高度：1.25 mm
子类别：Digital Potentiometers标称供电电压：3 V
表面贴装：YES技术：CMOS
标称温度系数：300 ppm/ °C温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40标称总电阻：10000 Ω
宽度：4.4 mmBase Number Matches：1

CAT5401Y-10-TE13 数据手册

 浏览型号CAT5401Y-10-TE13的Datasheet PDF文件第2页浏览型号CAT5401Y-10-TE13的Datasheet PDF文件第3页浏览型号CAT5401Y-10-TE13的Datasheet PDF文件第4页浏览型号CAT5401Y-10-TE13的Datasheet PDF文件第5页浏览型号CAT5401Y-10-TE13的Datasheet PDF文件第6页浏览型号CAT5401Y-10-TE13的Datasheet PDF文件第7页 
Preliminary Information  
E
CAT5401  
Quad Digitally Programmable Potentiometers (DPP™)  
with 64 Taps and SPI Interface  
TM  
FEATURES  
■ Automatic recall of saved wiper settings at  
■ Four linear-taper digitally programmable  
power up  
potentiometers  
■ 2.5 to 6.0 volt operation  
■ 64 resistor taps per potentiometer  
■ Standby current less than 1µA  
■ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ  
■ 1,000,000 nonvolatile WRITE cycles  
■ 100 year nonvolatile memory data retention  
■ 24-lead SOIC, 24-lead TSSOP and BGA  
■ Potentiometer control and memory access via  
SPI interface: Mode (0, 0) and (1, 1)  
■ Low wiper resistance, typically 80Ω  
■ Nonvolatile memory storage for up to four wiper  
■ Commercial and industrial temperature ranges  
settings for each potentiometer  
DESCRIPTION  
registers is via a SPI serial bus. On power-up, the  
contents of the first data register (DR0) for each of the  
four potentiometers is automatically loaded into its  
respective wiper control register.  
The CAT5401 is four Digitally Programmable  
Potentiometers (DPPs™) integrated with control logic  
and 16 bytes of NVRAM memory. Each DPP consists of  
aseriesof63resistiveelementsconnectedbetweentwo  
externallyaccessibleendpoints.Thetappointsbetween  
eachresistiveelementareconnectedtothewiperoutputs  
with CMOS switches. A separate 6-bit control register  
(WCR)independentlycontrolsthewipertapswitchesfor  
each DPP. Associated with each wiper control register  
are four 6-bit non-volatile memory data registers (DR)  
used for storing up to four wiper settings. Writing to the  
wiper control register or any of the non-volatile data  
The CAT5401 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications.Itisavailableinthe0°Cto70°Ccommercial  
and -40°C to 85°C industrial operating temperature  
ranges and offered in a 24-lead SOIC and TSSOP  
package or in the chip scale BGA.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
SOIC Package (J, W)  
TSSOP Package (U, Y)  
R
R
H3  
R
R
H2  
H1  
H0  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
NC  
R
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
WP  
CS  
R
V
1
SI  
1
CC  
R
2
A
2
L3  
L0  
1
R
R
A
R
R
3
R
R
3
H3  
W0  
CS  
SCK  
R
R
R
H0  
L1  
W0  
W1  
W2  
W3  
WIPER  
CONTROL  
REGISTERS  
SPI BUS  
INTERFACE  
R
R
V
4
4
W3  
H0  
L0  
W0  
CS  
H1  
SI  
SO  
5
R
5
0
W1  
SO  
WP  
SI  
6
GND  
NC  
6
CC  
CAT  
5401  
CAT  
5401  
HOLD  
SCK  
NC  
7
7
WP  
A0  
A1  
R
R
R
A
A
8
R
8
NONVOLATILE  
DATA  
REGISTERS  
1
L3  
CONTROL  
LOGIC  
W2  
R
R
9
R
9
L2  
H3  
W3  
L1  
H2  
R
R
R
10  
11  
12  
R
10  
11  
12  
H2  
H1  
L2  
R
R
SCK  
W2  
W1  
0
R
R
L3  
R
L1  
R
L2  
L0  
NC  
SO  
GND  
HOLD  
1
2
3
4
R
CS  
WP  
A
R
L1  
W0  
1
A
R
SI  
R
W1  
L0  
B
C
D
E
F
V
R
R
V
CC  
H0  
H3  
H1  
H2  
SS  
NC  
BGA  
NC  
R
R
R
SO  
HOLD  
SCK  
R
W2  
L3  
R
A
R
L2  
W3  
0
Top View - Bump Side Down  
1
© 2003 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Document No. 2010, Rev. E  
1234567...16

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