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CAT5401WI-25-TE13

更新时间： 2024-11-01 22:10:39
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Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and SPI Interface

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CAT5401WI-25-TE13 数据手册

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E
CAT5401  
Quad Digitally Programmable Potentiometers (DPP™)  
with 64 Taps and SPI Interface  
TM  
FEATURES  
■ Automatic recall of saved wiper settings at  
■ Four linear-taper digitally programmable  
power up  
potentiometers  
■ 2.5 to 6.0 volt operation  
■ 64 resistor taps per potentiometer  
■ Standby current less than 1µA  
■ 1,000,000 nonvolatile WRITE cycles  
■ 100 year nonvolatile memory data retention  
■ 24-lead SOIC, 24-lead TSSOP and BGA  
■ Industrial temperature range  
■ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ  
■ Potentiometer control and memory access via  
SPI interface: Mode (0, 0) and (1, 1)  
■ Low wiper resistance, typically 80Ω  
■ Nonvolatile memory storage for up to four wiper  
settings for each potentiometer  
DESCRIPTION  
wiper control register or any of the non-volatile data  
registers is via a SPI serial bus. On power-up, the  
contents of the first data register (DR0) for each of the  
four potentiometers is automatically loaded into its  
respective wiper control register.  
The CAT5401 is four Digitally Programmable  
Potentiometers (DPPs™) integrated with control logic  
and 16 bytes of NVRAM memory. Each DPP consists of  
aseriesof63resistiveelementsconnectedbetweentwo  
externallyaccessibleendpoints.Thetappointsbetween  
eachresistiveelementareconnectedtothewiperoutputs  
with CMOS switches. A separate 6-bit control register  
(WCR)independentlycontrolsthewipertapswitchesfor  
each DPP. Associated with each wiper control register  
are four 6-bit non-volatile memory data registers (DR)  
used for storing up to four wiper settings. Writing to the  
The CAT5401 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
SOIC Package (J, W)  
TSSOP Package (U, Y)  
R
R
H3  
R
R
H2  
H1  
H0  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
NC  
R
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
WP  
CS  
R
V
1
SI  
1
CC  
R
2
A
2
L3  
L0  
1
R
R
A
R
R
3
R
R
3
H3  
W0  
H0  
L1  
CS  
SCK  
R
R
R
W0  
W1  
W2  
W3  
WIPER  
CONTROL  
REGISTERS  
SPI BUS  
INTERFACE  
R
R
V
4
4
W3  
H0  
W0  
CS  
H1  
SI  
SO  
5
R
5
0
L0  
W1  
SO  
WP  
SI  
6
GND  
NC  
6
CC  
CAT  
5401  
CAT  
5401  
HOLD  
SCK  
NC  
7
7
WP  
A0  
A1  
R
R
R
A
A
8
R
8
NONVOLATILE  
DATA  
REGISTERS  
1
L3  
CONTROL  
LOGIC  
W2  
R
L2  
R
9
R
9
H3  
W3  
L1  
H2  
R
R
H2  
R
10  
11  
12  
R
10  
11  
12  
H1  
L2  
R
W2  
R
W1  
SCK  
0
R
R
L3  
R
L1  
R
L2  
L0  
NC  
SO  
GND  
HOLD  
1
2
3
4
R
CS  
WP  
A
R
L1  
W0  
1
A
R
SI  
R
W1  
L0  
B
C
D
E
F
V
R
R
V
CC  
H0  
H3  
H1  
H2  
SS  
NC  
BGA  
NC  
R
R
R
SO  
HOLD  
SCK  
R
W2  
L3  
R
W3  
A
R
L2  
0
Top View - Bump Side Down  
1
© 2004 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Document No. 2010, Rev. F  
1234567...18

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