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CAT5269YI-00

更新时间： 2024-09-08 06:46:15
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安森美 - ONSEMI /
页数 文件大小 规格书
16页 241K
描述
Dual Digitally Programmable Potentiometers with 256 Taps and 2-wire Interface

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CAT5269YI-00 数据手册

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CAT5269  
Dual Digitally Programmable Potentiometers  
(DPP™) with 256 Taps and 2-wire Interface  
FEATURES  
DESCRIPTION  
„ Four linear taper digitally programmable  
The CAT5269 is two digitally programmable poten–  
tiometers (DPPs™) integrated with control logic and  
18 bytes of NVRAM memory. Each DPP consists of a  
series of resistive elements connected between two  
externally accessible end points. The tap points  
between each resistive element are connected to the  
wiper outputs with CMOS switches. A separate 8-bit  
control register (WCR) independently controls the  
wiper tap switches for each DPP. Associated with  
each wiper control register are four 8-bit non-volatile  
memory data registers (DR) used for storing up to four  
wiper settings. Writing to the wiper control register or  
any of the non-volatile data registers is via a 2-wire  
serial bus. On power-up, the contents of the first data  
register (DR0) for each of the four potentiometers is  
automatically loaded into its respective wiper control  
registers.  
potentiometers  
„ 256 resistor taps per potentiometer  
„ End to end resistance 50kΩ or 100kΩ  
„ Potentiometer control and memory access via  
2-wire interface (I2C like)  
„ Low wiper resistance, typically 100Ω  
„ Nonvolatile memory storage for up to four  
wiper settings for each potentiometer  
„ Automatic recall of saved wiper settings at  
power up  
„ 2.5 to 6.0 volt operation  
„ Standby current less than 1µA  
„ 1,000,000 nonvolatile WRITE cycles  
„ 100 year nonvolatile memory data retention  
„ 24-lead SOIC and TSSOP packages  
„ Industrial temperature range  
The CAT5269 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications. It is available in the -40ºC to 85ºC  
industrial operating temperature ranges and offered in  
a 24-lead SOIC and TSSOP package.  
For Ordering Information details, see page 15.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
SOIC (W)  
TSSOP (Y)  
R
H0  
R
H1  
NC  
A0  
1
2
3
4
5
6
7
8
9
24 A3  
WIPER  
CONTROL  
REGISTERS  
2-WIRE BUS  
INTERFACE  
SCL  
SDA  
23 SCL  
22 NC  
21 NC  
20 NC  
19 NC  
18 GND  
17 RW1  
16 RH1  
15 RL1  
14 A1  
R
R
W0  
NC  
NC  
NC  
NC  
VCC  
RLO  
RHO  
W1  
WP  
A0  
A1  
A2  
A3  
NONVOLATILE  
DATA  
REGISTERS  
CONTROL  
LOGIC  
R
L0  
R
L1  
RWO 10  
A2 11  
¯¯¯  
WP  
12  
13 SDA  
© 2008 SCILLC. All rights reserved.  
Characteristics subject to change without notice  
1
Doc. No. MD-2123 Rev. E  
1234567...16

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CAT5269YI-00 替代型号

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