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CAT5269UI-50TE13 PDF预览

CAT5269UI-50TE13

更新时间: 2024-02-13 05:16:04
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描述
Dual Digitally Programmable Potentiometers (DPP) with 256 Taps and 2-wire Interface

CAT5269UI-50TE13 数据手册

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E
CAT5269  
Dual Digitally Programmable Potentiometers (DPP™)  
with 256 Taps and 2-wire Interface  
TM  
FEATURES  
Two linear taper digitally programmable poten-  
Automatic recall of saved wiper settings at  
tiometers  
power up  
256 resistor taps per potentiometer  
End to end resistance 50kor 100kΩ  
2.5 to 6.0 volt operation  
Standby current less than 1 µA  
1,000,000 nonvolatile WRITE cycles  
100 year nonvolatile memory data retention  
24-lead SOIC and TSSOP packages  
Industrial temperature range  
Potentiometer control and memory access via  
2-wire interface (I2C like)  
Low wiper resistance, typically 100Ω  
Nonvolatile memory storage for up to four  
wiper settings for each potentiometer  
DESCRIPTION  
The CAT5269 is two digitally programmable  
potentiometers (DPPs™) integrated with control logic  
and 18 bytes of NVRAM memory. Each DPP consists of  
a series of resistive elements connected between two  
externallyaccessibleendpoints.Thetappointsbetween  
each resistive element are connected to the wiper  
outputs with CMOS switches. A separate 8-bit control  
register (WCR) independently controls the wiper tap  
switches for each DPP. Associated with each wiper  
control register are four 8-bit non-volatile memory data  
registers (DR) used for storing up to four wiper settings.  
Writing to the wiper control register or any of the  
non-volatile data registers is via a 2-wire serial bus. On  
power-up, the contents of the first data register (DR0)  
for each of the four potentiometers is automatically  
loaded into its respective wiper control registers.  
The CAT5269 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications.Itisavailableinthe-40˚Cto8Cindustrial  
operating temperature range and offered in a 24-lead  
SOIC and TSSOP packages.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
SOIC Package (J, W)  
TSSOP Package (U, Y)  
R
R
H1  
H0  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1
NC  
A0  
A3  
2
SCL  
NC  
3
NC  
NC  
NC  
NC  
WIPER  
CONTROL  
REGISTERS  
SCL  
SDA  
2-WIRE BUS  
INTERFACE  
4
NC  
R
R
W0  
W1  
5
NC  
6
NC  
CAT  
5269  
7
V
GND  
CC  
WP  
8
R
R
R
R
W1  
H1  
L1  
L0  
9
R
R
H0  
A0  
A1  
A2  
A3  
10  
11  
12  
NONVOLATILE  
DATA  
REGISTERS  
W0  
A2  
CONTROL  
LOGIC  
A1  
WP  
SDA  
R
R
L1  
L0  
© 2004 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Document No. 2123, Rev. B  
1

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