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CAT5269BI-50TE13

更新时间： 2024-01-02 22:02:44
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Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface

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CAT5269BI-50TE13 数据手册

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E
CAT5419  
DualDigitallyProgrammablePotentiometers(DPP™)with  
64 Taps and 2-wire Interface  
TM  
FEATURES  
■ Two linear-taper digital potentiometers  
■ 64 resistor taps per potentiometer  
■ Recall of wiper settings at power up  
■ 2.5 to 6.0 volt operation  
■ End-to-end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ  
■ Standby current less than 1µA  
■ 1,000,000 nonvolatile WRITE cycles  
■ Potentiometer control and memory access via  
2-wire interface (I2C like)  
■ 100 year nonvolatile memory data retention  
■ 24-lead SOIC, 24-lead TSSOP and BGA  
■ Write protection for data register  
■ Low wiper resistance, typically 80Ω  
■ Four non-volatile wiper settings for each  
potentiometer  
DESCRIPTION  
firstdataregister(DR0)foreachofthetwopotentiometers  
is automatically loaded into its respective wiper control  
registers (WCR).  
The CAT5419 is two Digitally Programmable  
Potentiometers (DPP™) integrated with control logic  
and 16 bytes of NVRAM memory.  
The Write Protection (WP) pin protects against  
inadvertent programming of the data register.  
A separate 6-bit control register (WCR) independently  
controlsthewipertappositionforeachDPP. Associated  
with each wiper control register are four 6-bit non-  
volatile memory data registers (DR) used for storing up  
tofourwipersettings.Writingtothewipercontrolregister  
or any of the non-volatile data registers is via a 2-wire  
serial bus (I2C-like). On power-up, the contents of the  
The CAT5419 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications.  
PIN CONFIGURATION  
FUNCTIONAL DIAGRAM  
SOIC Package (J, W)  
TSSOP Package (U, Y)  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
NC  
NC  
NC  
NC  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
WP  
V
1
SDA  
1
CC  
R
R
H1  
H0  
A
2
R
2
A
1
2
L0  
R
W0  
R
3
R
L1  
3
H0  
R
R
V
R
W0  
4
R
H1  
4
H0  
A
0
WIPER  
CONTROL  
REGISTERS  
A
2
5
R
W1  
5
L0  
SCL  
SDA  
2-WIRE BUS  
INTERFACE  
NC  
WP  
6
GND  
NC  
6
CC  
CAT  
5419  
CAT  
5419  
R
R
A
3
NC  
SDA  
7
7
W0  
W1  
SCL  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
A
8
NC  
8
1
WP  
R
9
NC  
9
L1  
R
10  
11  
12  
NC  
10  
11  
12  
H1  
A0  
A1  
A2  
A3  
NONVOLATILE  
DATA  
REGISTERS  
CONTROL  
LOGIC  
A
0
R
W1  
SCL  
NC  
GND  
A
3
1
2
3
4
R
L0  
R
L1  
R
W0  
A
A
R
L1  
2
1
A
R
WP  
SDA  
R
W1  
L0  
B
C
D
E
F
V
R
H0  
R
H1  
V
SS  
CC  
BGA  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
A
3
A
SCL  
0
Top View - Bump Side Down  
1
© 2004 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Document No. 2115, Rev. F  
1234567...18

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