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CAT5261

更新时间: 2024-11-29 06:46:15
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安森美 - ONSEMI /
页数 文件大小 规格书
15页 225K
描述
Dual Digitally Programmable Potentiometers (DPP™) with 256 Taps and SPI Interface

CAT5261 数据手册

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CAT5261  
Dual Digitally Programmable Potentiometers  
(DPP™) with 256 Taps and SPI Interface  
FEATURES  
DESCRIPTION  
„ Two linear-taper digitally programmable  
The CAT5261 is two Digitally Programmable  
Potentiometers (DPPs™) integrated with control logic  
and 8 bytes of NVRAM memory. Each DPP consists of  
a series of resistive elements connected between two  
externally accessible end points. The tap points  
between each resistive element are connected to the  
wiper outputs with CMOS switches. A separate 8-bit  
control register (WCR) independently controls the wiper  
tap switches for each DPP. Associated with each wiper  
control register are four 8-bit non-volatile memory data  
registers (DR) used for storing up to four wiper settings.  
Writing to the wiper control register or any of the non-  
volatile data registers is via a SPI serial bus. On power-  
up, the contents of the first data register (DR0) for each  
of the potentiometers is automatically loaded into its  
respective wiper control register.  
potentiometers  
„ 256 resistor taps per potentiometer  
„ End to end resistance 50 kor 100 kΩ  
„ Potentiometer control and memory access via  
SPI interface  
„ Low wiper resistance, typically 100  
„ Nonvolatile memory storage for up to four  
wiper settings for each potentiometer  
„ Automatic recall of saved wiper settings at  
power up  
„ 2.5 to 6.0 volt operation  
„ Standby current less than 1µA  
„ 1,000,000 nonvolatile WRITE cycles  
„ 100 year nonvolatile memory data retention  
„ 24-lead SOIC and 24-lead TSSOP  
„ Industrial temperature range  
The CAT5261 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications. It is available in the -40°C to 85°C  
industrial operating temperature range and offered in  
a 24-lead SOIC and TSSOP package.  
„ Industrial temperature range  
For Ordering Information details, see page 14.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
SOIC/TSSOP (W, Y)  
¯¯¯¯¯  
R
H0  
R
H1  
CS  
SCK  
SI  
SO  
A0  
1
2
3
4
5
6
7
8
24  
HOLD  
WIPER  
CONTROL  
REGISTERS  
SPI BUS  
INTERFACE  
23 SCK  
22 NC  
21 NC  
20 NC  
19 NC  
18 GND  
17 RW1  
R
R
W0  
SO  
NC  
NC  
NC  
NC  
VCC  
RL0  
W1  
CAT  
5261  
WP  
A0  
A1  
NONVOLATILE  
DATA  
REGISTERS  
CONTROL  
LOGIC  
HOLD  
R
L0  
R
L1  
RH0  
9
16 RH1  
RW0 10  
15 RL1  
14 A1  
13 SI  
¯¯¯  
CS  
11  
12  
¯¯¯  
WP  
© 2009 SCILLC. All rights reserved.  
Characteristics subject to change without notice  
1
Doc. No. MD-2122 Rev. G  

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