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CAT5259UI-00TE13 PDF预览

CAT5259UI-00TE13

更新时间: 2024-11-06 22:17:35
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CATALYST /
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描述
Quad Digitally Programmable Potentiometers (DPP) with 256 Taps and 2-wire Interface

CAT5259UI-00TE13 数据手册

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E
CAT5259  
Quad Digitally Programmable Potentiometers (DPP™)  
with 256 Taps and 2-wire Interface  
TM  
FEATURES  
Four linear taper digitally programmable  
Automatic recall of saved wiper settings at  
potentiometers  
power up  
256 resistor taps per potentiometer  
End to end resistance 50kor 100kΩ  
2.5 to 6.0 volt operation  
Standby current less than 1 µA  
1,000,000 nonvolatile WRITE cycles  
100 year nonvolatile memory data retention  
24-lead SOIC and 24-lead TSSOP packages  
Industrial temperature range  
Potentiometer control and memory access via  
2-wire interface (I2C like)  
Low wiper resistance, typically 100Ω  
Nonvolatile memory storage for up to four  
wiper settings for each potentiometer  
DESCRIPTION  
The CAT5259 is four digitally programmable  
potentiometers (DPPs™) integrated with control logic  
and 16 bytes of NVRAM memory. Each DPP consists of  
a series of resistive elements connected between two  
externallyaccessibleendpoints.Thetappointsbetween  
eachresistiveelementareconnectedtothewiperoutputs  
with CMOS switches. A separate 8-bit control register  
(WCR)independentlycontrolsthewipertapswitchesfor  
each DPP. Associated with each wiper control register  
are four 8-bit non-volatile memory data registers (DR)  
used for storing up to four wiper settings. Writing to the  
wiper control register or any of the non-volatile data  
registers is via a 2-wire serial bus. On power-up, the  
contents of the first data register (DR0) for each of the  
four potentiometers is automatically loaded into its  
respective wiper control registers.  
The CAT5259 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications.Itisavailableinthe0˚Cto7Ccommercial  
and -40˚C to 85˚C industrial operating temperature  
ranges and offered in a 24-lead SOIC and TSSOP  
package.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
SOIC/TSSOP Package (J, W/U, Y)  
R
R
H3  
R
H1  
R
H2  
H0  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1
NC  
A0  
A3  
2
SCL  
RL2  
RH2  
R
R
R
W0  
W1  
W2  
W3  
3
R
WIPER  
CONTROL  
REGISTERS  
SCL  
SDA  
W3  
H3  
L3  
2-WIRE BUS  
INTERFACE  
4
R
R
5
R
W2  
WP  
6
NC  
NC  
CAT  
5259  
7
V
GND  
CC  
A0  
A1  
A2  
A3  
NONVOLATILE  
DATA  
REGISTERS  
8
CONTROL  
LOGIC  
R
R
W1  
L0  
9
R
R
R
R
H0  
H1  
10  
11  
12  
R
L1  
W0  
A2  
A1  
R
R
L3  
R
R
L2  
L1  
L0  
WP  
SDA  
© 2004 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Document No. 2000, Rev. F  
1

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